摘要：In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack.technique, hybrid multi-threshold CMOS partial stack.technique, hybrid super cutoff complete stack.technique and hybrid super cutoff partial stack.technique, have been proposed to reduce the subthreshold leak.ge power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leak.ge power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leak.ge power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leak.ge power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack.technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leak.ge power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack.technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack.technique proved to perform better in terms of subthreshold leak.ge power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.