摘要：Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based ***,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay *** has been controlled digitally with a switch network of NMOS and PMOS *** three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μ*** frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been *** phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed *** with earlier reported circuits have been made and the present approach shows advantages over previous circuits.