摘要：The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET system which can easily design the timing control. Each channel consists of a charge preamplifier, slow/fast shaper, discriminator and an analog memory. There are an ADC and a TDC to process the energy information and time information for each channel at the same time. In this paper, the whole system signals flow is all simulated by MATLAB. The simulation results show that the proposed system can process slender current from the detector and achieve the energy and time information. The proposed architecture can be applied to high-resolution PET imaging systems with multi-channel ASICs.

摘要：This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity

摘要：In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.

摘要：研制成功一款彩屏手机用262144色132RGB×176-dot分辨率TFT-LCD单片集成驱动控制电路芯片,提出了基于低/中/高混合电压工艺、数模混合信号VLSI显示驱动芯片的设计及其验证方法,开发了SRAM访问时序冲突解决电路、二级输出驱动电路和动态负载补偿输出缓冲电路等新型电路结构,有效减小了电路的功耗和面积,抑制了回馈电压的影响,提高了液晶显示画面质量。采用0.25μm混合电压CMOS工艺实现的工程样片一次性流片成功,整个芯片的静态功耗约为5mW,输出灰度电压的安定时间小于30μs,芯片性能指标均达到设计要求。

摘要：A top-down design methodology is proposed for the design of TFT-LCD one-chip driver ICs,and a 260k color, 176RGB× 220-dot TFT-LCD one-chip driver IC is successfully developed with silicon verification. This IC is a typical mixed-signal VLSI and is implemented by a 0.18μm HV CMOS process. The static power dissipation is about 5mW for 260k color display mode,and the settling time of the output grayscale voltages within 0.2% error is less than 26μs.

摘要：为了解决传统功率通路中肖特基二极管导通损耗较大的问题,设计了一款高精度可编程限流双通道理想二极管功率通路,基于0.18μm BiCMOS工艺进行了流片验证.采用了新颖的自适应电源选通控制电路,避免PMOS功率管的寄生体二极管导通的风险,并使PMOS功率管导通阻抗仅为40 mΩ.芯片实测结果表明:单个理想二极管功率通路在4 A电流条件下,-40°~125°温度范围内传输效率达到92%以上;而且电路内部集成了高精度可编程限流保护电路,单个通道实现了0.15~4 A范围内限流阈值调节.

摘要：在分析各种超宽带(UWB)接收机系统结构的基础上,提出了一种低功耗IR-UWB接收机结构。该结构基于非相干通信机制,使用自混频技术和脉冲宽度调制方式(PPM)。在该结构中,低噪声放大器(LNA)的低功耗优化是系统低功耗实现的关键。综合分析各种宽带LNA结构,提出了一种低功耗LNA设计。该LNA采用65 nmCMOS标准工艺实现,设计带宽为3.1～5 GHz,电源电压为1 V,功耗为1.5 mW。测试结果表明,该宽带LNA的输入阻抗匹配优于-10 dB,增益高达14.5 dB,而噪声系数为5.85 dB。

摘要：针对手机用TFT-LCD驱动控制芯片的应用环境具有高噪声、毛刺持续时间长的特点,提出一种采用电容充放电延时和反馈技术的抑制毛刺复位接口电路。该电路可以消除持续时间长达数微秒的单个毛刺。另外,通过自动选择不同的充放电路径,可实现不同的延迟时间,从而可以消除毛刺的累积效益。设计的复位接口电路已经成功应用于176RGB×220分辨率、26万色手机用TFT-LCD驱动控制芯片。采用0.18μmCMOS中压工艺的HSPICE仿真以及工程样片流片结果表明,所设计的复位接口电路的性能完全满足TFT-LCD驱动控制芯片的复杂应用环境要求,并且具有面积开销较小的特点。

摘要：在空间应用和核辐射环境中,单粒子翻转(SEU)效应严重影响SRAM的可靠性。采用错误检测与校正(EDAC)和版图设计加固技术研究和设计了一款抗辐射SRAM芯片,以提高SRAM的抗单粒子翻转效应能力。内置的EDAC模块不仅实现了对存储数据"纠一检二"的功能,其附加的存储数据错误标志位还简化了SRAM的测试方案。通过SRAM原型芯片的流片和测试,验证了EDAC电路的功能。与三模冗余技术相比,所设计的抗辐射SRAM芯片具有面积小、集成度高以及低功耗等优点。

摘要：提出了一种应用于数字DC-DC变换器的高精度定点数字控制器的设计方法;在数字控制器的控制率运算中,将浮点数格式的控制参数转化为定点数格式,从而达到简化硬件电路的目的;该设计方法应用于降压型数字DC-DC变换器的设计中,并完成了基于FPGA的测试和验证;在500kHz的开关频率下,输出电压纹波为14mV,对于±0.5A的负载电流跳变,控制器响应时间约为330μs。测试结果表明,该设计方法在保持控制精度的前提下,可简化硬件电路的设计复杂度,并改善系统的瞬态性能。