摘要：The rap.d dev.lop.ent in the digital circuit design enhances the ap.lications on v.ry large scale integration era. Encoders are one am.ng the digital circuits found in all com.unication system.. The p.lar encoding is m.inly m.ant for its channel achiev.ng p.op.rty. It finds its ap.lication in com.unications, sensing and inform.tion theory. This coding p.op.sed b. Erdal Arikan is significant b.cause of its zero error floors and sim.0}e architecture for hardware im.0}em.ntation. In this p.p.r, a folded p.lar encoder is designed to start from.the fully p.rallel architecture and p.oceeds with its data flow grap., delay requirem.nt calculation, lifetim. analysis and register allocation, which results in a v.ry large scale integration architecture with m.nim.m.hardware utilization. The results are sim.lated for 4 and 8 p.rallel folded 32-b.t p.lar encoder using Xilinx 14.6 ISIm.and im.0}em.nted in v.rtex 5 field p.ogram.ab.e gate array. A com.0}rison is m.de on fully p.rallel and v.rious folding techniques b.sed on their resource utilization.