摘要：A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS *** was fully integrated excluding the inductors and the output matching *** a single 3.3V supply voltage,the off-chip bonding test results indicated that the circuit has a smallsignal gain of more than 24dB,the input and output reflectance are less than- 24dB and-10dB,re-spectively,and the maximal output power is 23.5 *** output power of 23.1 dBm,the PAE(poweradded efficiency)is 30.2%,the IMD2 and IMD3 are less than- 32 dBc and-46 dBc,*** chip size is 1.27mm ×0.9mm.

摘要：A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.

摘要：A CMOS quadrature LC-tank voltage-controlled oscillator topology which uses a planar spiral transformer as coupling elements has been implemented in mixed-signal and RF 1P6M 0.18μm CMOS technology of SMIC. The measured phase noise is -125.7 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.6 GHz while the VCO core circuit draws only of 10 mW from a 1.8 V supply. The measured phase error is approximately 1.5° based on the time domain outputs and the output power is about -2 dBm. The VCO can cover the frequency range of 4.36-4.68 GHz. The tuning range is 320 MHz （7.0%） and the FOM is -189 dB.

摘要：A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(VSR)optoelectronic integrated circuit(OEIC)*** dominant pole of the input node is shifted up to a high frequency,and thus the bandwidth of the CMOS DNFFCG TIA is ***,two negative feedback loops are used to reduce the input impedance and further increase the *** proposed TIA was fabricated using TSMC 0.18 jxm CMOS *** whole circuit has a compact chip area,the core area of which is only 0.003 6 *** power consumption is 14.6 mW excluding 2-stage differential *** test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1 8 V supply voltage and its trans-impedance gain is 49.2 *** measured average equivalent input noise current density is 28.1 pA H *** the same process conditions,the DNFFCG has better gain bandwidth product compared with those in the published papers.

摘要：介绍了用于SDH系统STM-64速率光发射机用的激光二极管/光调制器驱动器集成电路的设计。电路采用法国OMMIC公司的0.2μm GaAs PHEMTs工艺设计并制造,可以驱动激光二极管和电吸收式调制器。电路由输入匹配电路、预放大电路、源极跟随器、主放大电路、电容耦合电流放大器和输出电路组成。电路芯片面积1.0mm×0.9mm。测试结果表明,电路采用单一正5V电源供电,直流功耗1.4W,可以在10Gb/s速率下正常工作,眼图良好。最高工作速率高于20Gb/s,输出电压幅度2.8V。

摘要：基于 DRM 标准,研究并设计了一种 DRM 广播接收机射频前端芯片的结构,该射频前端选用了上边注入、固定中频的二次正交混频低中频结构。经理论推导,给出了该结构的4种镜像抑制比(IRR)与相位误差或幅度误差的定量关系。经综合考虑镜像干扰、互调干扰、低频本振谐波干扰、寄生低频噪声等因素与中频频率的定量或定性关系,确定了系统频率规划。该结构中除射频滤波器外其它模块均为片上实现,继承了低中频结构的所有优点。理论分析与仿真结果表明,采用该频率规划的接收机射频前端完全满足 DRM接收机射频前端的设计要求。此频率规划设计为射频前端芯片的电路级设计成功奠定了理论基础。

摘要：采用了国内0．6μm标准CMOS工艺设计实现了一种单片集成的分布式放大器。放大器采用四级级联结构，单元电路采用管联（cascode）结构以提高隔离度。在输人输出端50Ω匹配情况下，测试得到的频带宽度为0．1～4.0GHz，增益为5.0±1.0dB，输入输出的回波损耗分别小于-10dB和-7dB。在5V供电下功耗约为110mW。

摘要：为满足电子系统对放大器的带宽性能要求，基于2μm砷化镓（GaAs）异质结双极晶体管（HBT）工艺设计了一种新的分布式放大器。设计采用了输入电容耦合技术和L型传输线结构，有效提升了放大器的频率性能。测试结果显示，该放大器的3dB带宽达到14GHz，在1．2GHz～10．5GHz频率范围内增益为6．6dB，带内增益平坦度为±0．5dB，输入回波损耗小于-14dB，输出回波损耗小于-8．8dB，表现出了高增益和大带宽的特性。

摘要：应用标准0.35μm SiGe BiCMOS工艺设计Colpitts压控振荡器。采用开环S参数计算电路指标,计算结果与测量结果符合较好。测量结果表明,在3.3V电源电压下,压控振荡器的频率范围覆盖340~400MHz,10kHz频偏处相位噪声为-91dBc/Hz,输出功率-3dBm。芯片面积550μm×300μm。

摘要：采用线性时变(LTV)模型分析了电压偏置型 CMOS LC 交叉耦合压控振荡器(VCO)的相位噪声。以相位噪声为优化目标,元件参数为设计变量,根据理论计算与仿真结果确定了晶体管宽长比和谐振腔电感的最佳值,完成了电路的优化过程。并以此优化结果为依据,用 0.18gm CMOS 工艺设计、实现了一个芯片面积为1.1mm×0.7rnm 的 LC 交叉耦合振荡器。测试结果表明,在1.8V 电源电压下,该压控振荡器的频率范围覆盖1150～1210 MHz,10kHz 频偏处相位噪声达到-89dBc/Hz,核心电流4.3mA,抑制相位噪声性能优于其他振荡器。