摘要：Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially *** behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also *** CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked *** simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is *** results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps *** core of the whole chip consumes 72 mA current from a 1.0V supply.

摘要：MaskROM在MCU设计应用中扮演着重要角色,而高速、高集成度是未来发展趋势。设计了一种混合结构MaskROM,兼有NAND的高集成度以及NOR的快速读出优点。子模块中串联的管子越多,集成度越高,但速度会降低。通过对行译码进行小的子模块划分,阵列被划分为多个子模块并联。选择每个子模块为5个MOS管串联,这样既能提高集成度又能保持快速读出的特点。在选中的子模块中,被进一步选中的WL(Word Line)为低,其他WL为高,串联的bit被导通的MOS管短路掉4行,WL为低的那一行MOS管关闭,从而其MOS管两端有没有被金属短接决定了cell是否产生电流。行译码的方式可以很容易地通过数学公式进行归纳和理解。SA采用伪差分方式,通过预设offset方式实现cell的快速读出。基于0.18μm 2P5M EEPROM工艺设计实现了一款32 K×34bit的MaskROM,芯片测试结果表明,在典型条件下其读出速度能达到170 MHz。