摘要：We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method,having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V,simulation results showed that the charge time is 35 ns in the proposed sense amplifier,and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications,and has a silicon area of only 240 μm2.

摘要：With the development of Ethernet systems and the growing capacity of modem silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethemet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Intemet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system＇s throughput. Our simulation results showed that the maximum throughput of Ethemet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethemet, and that using only one chip can realize that many electronic devices access to the Intemet directly and get high performance.

摘要：It is an important challenge to implement a lowcost power analysis immune advanced encryption standard （AES） circuit. The previous study proves that substitution boxes （S-Boxes） in AES are prone to being attacked, and hard to mask for its non-linear characteristic. Besides, large amounts of circuit resources in chips and power consumption are spent in protecting S-Boxes against power analysis. Thus, a novel power analysis immune scheme is proposed, which divides the data-path of AES into two parts： inhomogeneous S-Boxes instead of fixed S-Boxes are selected randomly to disturb power and logic delay in the non-linear module; at the same time, the general masking strategy is applied in the linear part of AES. This improved AES circuit was synthesized with united microelectronics corporation （UMC） 0.25 μm 1.8 V complementary metal-oxide-semiconductor （CMOS） standard cell library, and correlation power analysis experiments were executed. The results demonstrate that this secure AES implementation has very low hardware cost and can enhance the AES security effectually against power analysis.

摘要：In this article, a parallel hardware processor is presented to compute elliptic curve scalar multiplication in polynomial basis representation. The processor is applicable to the operations of scalar multiplication by using a modular arithmetic logic unit （MALU）. The MALU consists of two multiplications, one addition, and one squaring. The two multiplications and the addition or squaring can be computed in parallel. The whole computations of scalar multiplication over GF（2^163） can be performed in 3 064 cycles. The simulation results based on Xilinx Virtex2 XC2V6000 FPGAs show that the proposed design can compute random GF（2^163） elliptic curve scalar multiplication operations in 31.17 μs, and the resource occupies 3 994 registers and 15 527 LUTs, which indicates that the crypto-processor is suitable for high-performance application.

摘要：本文介绍了一种EFM/EFM +解调器的设计和实现 .该解调器用于DVD光盘伺服控制 ,对读入的CD和DVD数据分别实现 14 - 8和 16 - 8解调 .文中通过对其工作原理和实际应用的分析 ,给出其最终实现方案 .并用Verilog硬件描述语言完成整个解调器的设计工作 .功能仿真和FPGA验证表明 ,设计成功 .

摘要：在产品概念解产生之后,应正确处理和表示设计过程中众多的设计信息。为此,建立了用于概念产品拓扑结构抽象表示的设计特征层次关系模型,提出了设计特征属性依存关系网模型。在这两个模型基础上,构造了用于表示概念产品设计信息的关系网。简要介绍了多色集合的主要思想,将概念解设计信息所包含的单元与多色集合的成分相对应,建立了概念产品设计信息基于多色集合的数学描述,以便于产品设计信息的存储、管理和随后设计工作的开展。

摘要：本文介绍了一种用于DVD ROM伺服控制芯片的内容干扰系统 (CSS)的硬件结构 .该系统通过在DVD驱动器和主机之间进行认证和对密钥进行加扰 ,可有效防止对DVD盘片的非法拷贝 .用VerilogHDL完成整个系统的设计 ,功能仿真结果表明 ,设计成功 .采用CMOS标准单元库的综合结果为 :CSS的最大时钟频率为 10 0MHZ ,面积为1.6 9mm2 (0 .2 5 μm) ,当CSS的频率为 10 0MHZ时功耗为 37.38mW ,其性能足以满足DVD应用 .

摘要：本文提出了一种高效的点乘调度策略和改进的双域高基Montgomery模乘算法,在此基础上设计了一种新型高性能可扩展公钥密码协处理器体系结构,并采用0.18μm 1P6M标准CMOS工艺实现了该协处理器,以支持RSA和ECC等公钥密码算法的计算加速.该协处理器通过扩展片上高速存储器和使用以基数为处理字长的方法,具有良好的可扩展性和较强的灵活性,支持2048位以内任意大数模幂运算以及576位以内双域任意椭圆曲线标量乘法运算.芯片测试结果表明其具有很好的加速性能,完成一次1024位模幂运算仅需197μs、GF(p)域192位标量乘法运算仅需225μs、GF(2m)域163位标量乘法运算仅需200.7μs.

摘要：低压、低功耗模拟集成电路设计受到多种因素的制约。围绕这些制约因素,回顾了国内外在模拟集成电路低压、低功耗设计领域的方法和技术的发展现状,主要涉及:轨对轨设计技术、亚阈值工作区技术、阈值电压降低技术、组合晶体管技术、横向BJT技术、SOI技术等。分析并比较了各种设计方法的优劣;并对模拟电路低压低功耗设计技术的发展趋势进行了展望。

摘要：构建了单供应商两分销商的VMI系统在需求随机情况下补货发货模型,并设计价格补贴机制协调VMI实施后供应商与分销商的利益.假定需求服从正态分布,总成本函数中考虑分段的运输成本函数,带安全库存及服务水平约束,供应商拥有库存的两级供应链.算例结果显示:实施VMI后采用基于共同补货期的时间协调决策模型能够降低供应链总成本,当采用等分法进行利益协调时,在设计的价格系数下,供应商与两分销商均有不同程度的获利.最后参数敏感性分析显示:分销商的缺货成本B的变化对价格系数影响不大,而分销商1的年需求均值υ_1、供应商处理分销商1每一个订单的固定成本S_(01)和实施VMI前分销商1每次的订单处理成本S_1的变化均会对价格系数产生不同程度的影响.