摘要：With the rapid development of integrated circuits [1], low power consumption has become a constant pursuiting goal of the designer in chip design. As the memory almost takes up the area of the chip, reducing memory power consumption will significantly reduce the overall power consumption of the chip;according to ISSCC’s 2014 report about technology trends discussions, there two points of the super-low power SRAM design: 1) design a more effective static and dynamic power control circuit for each key module of SRAM;2) ensure that in the case of the very low VDD min, SRAM can operating reliably and stably. This paper makes full use reliable of 8T cell, and the single-port sense amplifier has solved problems in the traditional 8T cell structure, making the new structure of the memory at a greater depth still maintain good performance and lower power consumption. Compared with the designed SRAM the SRAM generated by commercial compiler, as the performance loss at SS corner does not exceed 10%, the whole power consumption could be reduced by 54.2%, which can achieve a very good effect of low-power design.

摘要：X处理器是我国自主设计的基于EPIC思想的高性能通用微处理器·介绍了8级流水线和OLSM执行模型,以很少的硬件代价克服了基本EPIC模型的局限性·设计了一种多分支预测结构,支持多条分支指令的并行执行,并通过判定执行减少分支指令的数目;设计了两级cache存储器,提出DTD低功耗设计方法,并通过前瞻执行隐藏访存的延迟·最后,展望了高性能通用微处理器的发展趋势·

摘要：功能模拟是设计高性能微处理器接口ＡＳＩＣ芯片的重要环节，目的是消除ＡＳＩＣ的功能性设计错误。为了更好地对ＡＳＩＣ芯片进行模拟，需要灵活、方便、能够体现微处理器行为的ＣＰＵ模型，文章将介绍了对一个ＣＰＵ行为模拟器的开发。

摘要：本文提出了一种新型的具有升降压功能的DC-DC控制器的设计方案,它工作在PWM/PFM控制方式下,用于对超级电容电池的供电进行控制。文中阐述了DC-DC控制器的发展背景和工作原理,从系统结构上对该芯片进行了研究设计和模拟验证,模拟结果表明该控制器很好的实现了不同负载下的高效率。

摘要：采用0.13μm标准CMOS工艺,全定制设计实现了一款8 kB(8 k*8 bit)的高速低功耗静态随机存取存储器(SRAM)。分析了影响存储器性能和功耗的原因,并在电路布局上做了改进,将两个3-8译码器进行拆分与重组,降低了互连线的延迟和耦合作用;同时,对灵敏放大器也做了改进。版图后仿真表明,在电源电压为1.2 V、温度为25℃的典型条件下,读1延时为766.37 ps,最大功耗为11.29 mW,功耗延时积PDP为8.65 pJ,实现了很好的性能。