摘要：The load power range of modern processors is greatly enlarged because many advanced power management techniques are employed, such as dynamic voltage frequency scaling, Turbo Boosting, and near-threshold voltage （NTV） technologies. However, because the efficiency of power delivery varies greatly with different load conditions, conventional power delivery designs cannot maintain high efficiency over the entire voltage spectrum, and the gained power saving may be offset by power loss in power delivery. We propose SuperRange, a wide operational range power delivery unit. SuperRange complements the power delivery capability of on-chip voltage regulator and off-chip voltage regulator. On top of SuperRange, we analyze its power conversion characteristics and propose a voltage regulator （VR） aware power management algorithm. Moreover, as more and more cores have been integrated on a singe chip, multiple SuperRange units can serve as basic building blocks to build, in a highly scalable way, more powerful power delivery subsystem with larger power capacity. Experimental results show SuperRange unit offers lx and 1.3x higher power conversion efficiency （PCE） than other two conventional power delivery schemes at NTV region and exhibits an average 70% PCE over entire operational range. It also exhibits superior resilience to power-constrained systems.

摘要：物理不可克隆函数(physical unclonable function,PUF)在信息安全领域的应用日益广泛.然而,仲裁型PUF作为一种典型的强PUF,因逻辑确定而易被建模攻击破解;弱PUF虽然对建模攻击免疫,但无法提供较多激励响应对.为解决此问题,提出了一种非确定性仲裁型PUF,通过结合仲裁型PUF和弱PUF,使非确定性仲裁型PUF的部分布尔逻辑关系取决于弱PUF的不确定性输出,以提高该PUF的逻辑不确定性,进而提高了其抗建模攻击能力.同时,在FPGA上的实验也表明,所提设计具有较高的随机性(50.6%)和稳定性(94.5%).

摘要：针对卷积神经网络FPGA加速器的资源分配与频率设置欠佳导致吞吐量受限的问题,提出一种面向吞吐量优化的自动化设计方法.首先将加速器的设计分为并行策略和频率设计,提出总体设计流程;然后将设计空间探索建模为线段分割问题,采用遗传算法及贪心算法求解;最后根据求解出的并行策略完成加速器的结构设计,根据求解出的预期运行频率对加速器的布局布线优化,使实际频率可以达到预期.对AlexNet及VGG-16模型在目标器件AlteraDE5a-Net的设计实验结果表明,文中方法能有效地提升资源使用效率并给出合理频率设置;相比于其他卷积神经网络FPGA加速器设计方法,该方法可提升AlexNet和VGG-16的吞吐量82.95%和66.19%.

摘要：针对仲裁器物理不可克隆函数(PUF)响应随机性难以保证的问题,提出具有内建自调整功能的仲裁器PUF设计,该设计包含激励产生模块、可调仲裁器PUF模块和自调整模块.首先在传统仲裁器PUF上增加由调整信号控制的时延调节电路,实现可调仲裁器PUF结构;然后用线性反馈移位寄存器实现激励产生模块,生成用于测试PUF随机性的激励;最后加入自调整模块,通过分析PUF响应的随机性自动调整时延调节电路的调整信号,提高可调仲裁器PUF的随机性.实验结果表明,经过自调整,在FPGA上实现的多个所提仲裁器PUF,其随机性的平均值为50.62%,标准差仅为0.5%,随机性得到有效提高.