摘要：Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.

摘要：Many kinds of devices with cam have been widely used in various mechanical equipments. However, non-equalization machining for spatial cam trough remains to be a difficult problem. This paper focuses on the analysis of running conditions and machining processes of spatial cam with oscillating follower. We point out the common errors in the biased distance cutting. By analyzing the motion of oscillating follower of spatial cam, we present a new 3D curve expansion model of spatial cam trough-outline. Based on this model, we have proposed a machining method for trochoidal milling with non-equalization diameter cutter. This new method has led to a creative and effective way for non-equalization diameter machining for spatial cam with oscillating follower.