摘要：A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M cmos advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-cmos design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm^2.

摘要：JESD204B是一种专用于高速串行数据传输的接口技术,有利于多通道间数据的准确传输和延迟保持确定不变。设计了一种超高速ADC专用数据同步数字电路,并提出了相应确定性延迟的验证方案,满足JESD204B协议要求。该同步电路成功应用于八通道2 GS/s-12 bit ADC芯片,每条通道5 Gbps的串行数据输出,并基于40nm cmos工艺实现流片。基于现场可编程逻辑门阵列7K325T的测试平台,对芯片性能进行验证,其有效位数达到9.63 bit,芯片能够正常工作,通道间数据传输的同步性符合预期,测试多颗芯片的延迟结果为101个采样时钟周期,保证了延迟的稳定一致。