摘要：A fully monolithic power amplifier （PA） for multi-mode front end IC integration is presented. The PA is fabricated in an IBM 7WL 0.18 μm SiGe bicmos process with all the matching networks integrated on a chip. After load-pull test to find the best power stage size and layout optimization, the measured results show that the PA can obtain a 24 dBm maximum output power at 2.4 GHz, the output 1 dB compression point is 21 dBm at 5 dBm input, and the PAE is 18%. This PA is complete on-chip tested without any bonding wires and on-board matching, targeting fully power module integration in multi-mode system on chip.

摘要：A low-noise amplifier （LNA） operated at 40 GHz is designed. An improved cascode configuration is proposed and the design of matching networks is presented. Short-circuited coplanar waveguides （CPWs） were used as inductors to achieve a high Q-factor. The circuit was fabricated in a 0.13-μm SiGe bicmos technology with a transistor transit frequency fT of 103 GHz. The chip area is 0.21mm^2. The LNA has one cascode stage with a-3 dB bandwidth from 34 to 44 GHz. At 40 GHz, the measured gain is 8.6dB; the input return loss, S11, is -16.2dB; and the simulated noise figure is 5 dB. The circuit draws a current of only 3 mA from a 2.5 V supply.

摘要：A wideband low-noise amplifier（LNA） with ESD protection for a multi-mode receiver is *** LNA is fabricated in a 0.18-μm SiGe bicmos process,covering the 2.1 to 6 GHz frequency *** optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point（IIP3） is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating *** overall power consumption is 8 mW at 2.5 V voltage supply.

摘要：A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe bicmos *** was fully integrated excluding the inductors and the output matching *** a single 3.3V supply voltage,the off-chip bonding test results indicated that the circuit has a smallsignal gain of more than 24dB,the input and output reflectance are less than- 24dB and-10dB,re-spectively,and the maximal output power is 23.5 *** output power of 23.1 dBm,the PAE(poweradded efficiency)is 30.2%,the IMD2 and IMD3 are less than- 32 dBc and-46 dBc,*** chip size is 1.27mm ×0.9mm.

摘要：根据bicmos电路的工作特点,提出三值bicmos电路的一般结构.应用传输电压开关理论,从开关级设计PNP-NPN-NPN型三值bicmos通用驱动电路,并运用此电路设计三值bicmos反相器电路.测量和模拟结果表明,所设计的电路具有理想的逻辑功能,电路结构简单,功耗小.该通用驱动电路结构可以应用于任何三值bicmos电路的设计中,设计方法简单可行.采用相同的设计思路还可以实现其他NPN和PNP组合的通用驱动电路,进而实现任意三值bicmos电路的设计.

摘要：提出了一种结构简单的采用 Bi CMOS线性区跨导和输入预处理电路的低压 Bi CMOS四象限模拟乘法器 ,详细分析了电路的结构和设计原理。设计采用典型的 1.2 μm Bi CMOS工艺 ,并给出了电路的 SPICE模拟结果。模拟结果表明 ,当电源电压为± 3V时 ,功耗小于 2 .5m W,线性输入电压范围大约± 2 V。当输入电压范围限于± 1.6 V时 ,总谐波失真和非线性误差均小于0 .8% ,- 3d B带宽大于 110 MHz。

摘要：提出了一款基于0.13μmSiGebicmos工艺设计、加工的340GHz在片背腔贴片天线.辐射贴片位于AM 金属层带状线馈线置于 LY 金属层并通过连接 AM 金属层和 LY 金属层的金属化通孔对辐射贴片馈电.通过设计连接 AM 金属层和 M1 金属层的金属化通孔形成谐振腔体展宽了天线阻抗带宽、提升了天线辐射性能.天线的仿真阻抗带宽(S11≤-10dB)为9.2GHz(335.6~344.8GHz).天线在340GHz处的仿真增益为3.2dBi.天线的整体尺寸为0.5×0.56mm2.

摘要：分析一个由bicmos构成的单端对数域积分器的频率特性和存在的局限性 .提出了一个工作在甲乙类状态的对数域全差分积分器 ,并采用跨导线性原理分析得到了其传递函数 ,分析了全差分积分器的频率特性和动态范围 .PSpice仿真结果说明 ,全差分对数域积分器具有较宽的频率调谐范围 ,能在 1～ 2V之间的低电压下工作 ,同时具有较大的动态范围 ,更适合于高频、低电压和大动态范围的滤波器设计 .

摘要：验证SiGe bicmos工艺线性器件的单粒子瞬态(Single Event Transient, SET)效应敏感性,选取典型运算放大器THS4304和稳压器TPS760进行了脉冲激光试验研究。试验中,通过能量逐渐逼近方法确定了其诱发SET效应的激光阈值能量,并通过逐点扫描的办法分析了器件内部单粒子效应敏感区域,并在此基础上分析了脉冲激光能量与SET脉冲的相互关系,获得了单粒子效应截面,为SiGe bicmos工艺器件在卫星电子系统的筛选应用以及抗辐射加固设计提供数据参考。

摘要：基于IBM 0.18μm SiGe bicmos标准工艺设计实现了一种高速、低功耗的光接收机前端模拟电路。接收机芯片包括调节型共源共栅(RGC)跨阻放大器(TIA)、四级限幅放大器(LA)和输出缓冲电路(buffer)。采用高跨导SiGe异质结双极晶体管(HBT)作为输入级的RGC TIA有效隔离了探测器结电容和输入寄生电容的影响,更好地拓展了光接收机的带宽。仿真结果表明,在1.8V电源电压供电下,驱动50Ω电阻和10pF电容负载时,光接收机前端的跨阻增益为76.67dB,-3dB带宽为2.1GHz。测试结果表明,光接收机前端电路的-3dB带宽为1.2GHz,跨阻增益为72.2dB,在误码率(BER)为10-9的条件下,光接收机实现了1.5Gbit/s的数据传输速率。在1.8V电源电压下,芯片功耗仅为44mW,芯片总面积为800μm×370μm。