摘要：目前,人工智能(AI)芯片在集成电路(IC)领域发展迅猛,但针对此类新型芯片的传统课堂教学方式对集成电路专业的本科教学存在理论抽象、教学难度大、软件操作复杂和产教脱离等问题.结合培养大纲和行业需求,提出一种基于人工突触芯片设计的集成电路新型教学方法.以cmos人工突触电路为例,其作为一种新型神经计算单元,被认作未来AI芯片设计的基础单元重要方向.相较传统cmos计算单元,在应对大数据处理时,能体现出明显的算力和能耗优势.引入业内先进cmos人工突触电路设计方法,借助产业界常用的Cadence Virtuoso集成电路仿真工具实现课堂教学创新,帮助学生建立集成电路设计理论与实践的紧密联系,实现了卓越教学成果,是一种有效的教学方法.

摘要：当前,老龄化的人口问题、老年人的监护问题等日益成为社会的课题。鉴于中国独特的养老习惯——以依赖家庭和养老机构的养老模式为主,老年人往往难以应对突发的棘手问题。现在的视频监控系统大多由人实时监控。不间断的监控方式涉及老人不易接受的个人隐私问题。为提高老年人的生活质量,文章设计一种基于视频的老年人智能安全监测系统。该系统在运作期间通过构建关键技术异常模式库,实现对这些异常模式的精准识别。这一举措旨在加速老年人安全监测技术的研发进程,拓宽其在实际应用中的推广范围。

摘要：This paper presents a low noise amplifier（LNA）,which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13μm RF-cmos *** circuit was analyzed and a new optimization method for a folded cascode LNA was *** results of the proposed circuit demonstrated a power gain of 14.13 dB,consuming 3 mW DC power,showing 1.96 dB NF and an input 1-dB compression point of -19.9 *** input power matching（S_（11）） and output power matching（S_（22）） were below -10 *** results indicate that this LNA is fully applicable to low voltage and low power applications.

摘要：A new optimization method of a source inductive degenerated low noise amplifier（LNA） with electrostatic discharge protection is *** can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also *** on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF cmos technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 *** DC current is 4 mA under a supply of 1.8 V.

摘要：A rotary traveling-wave oscillator（RTWO） targeted at 5.8 GHz band operation is designed and fabricated using standard 0.18μm cmos *** simulation and measurement results are *** chip size including pads is 1.5×1.5 mm^*** measured output power at a frequency of 5.285 GHz is 6.68 dBm,with a phase noise of-102 dBc/Hz at 1 MHz offset from the carrier.

摘要：Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm cmos process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.

摘要：A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm cmos technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET（IMOS） varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range（FTR） of 18.4%and a phase noise of –101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.

摘要：An ultra-wideband （3.1-10.6 GHz） low-noise amplifier using the 0.18μm cmos process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW （without output buffer for measurement） with a 1.8 V power supply and occupies 0.88 mm^2.

摘要：With more scaling, the speed of than 40 years Moore cmos transistors is around 100 GHz. Such fact makes it possible to realize mm-wave circuits in cmos. However, with the target of achieving broadband and power-efficient operation, 60 GHz cmos RF transceiver faces severe challenges. After reviewing the technology issues, regarding the 60 GHz applications, this paper discusses design challenges both from the system and the building block levels, and also presents some simulated or measured circuits results.

摘要：This paper presents the design of 0.5 V multi-gigahertz cascode cmos LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 μm cmos technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.