摘要：The double gate （DG） silicon MOSFET with an extremely short-channel length has the appropriate fea- tures to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill meth- ods and models in terms of their complexity and computation time （self-consistent, quantum computations ）. Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic cir- cuit design. The approach is general and thus is suitable for any type ofnanoscale structure investigation problems in the nanotechnology industry.

摘要：Since traditional fault tolerance methods of electronic systems are based on redundant fault tolerance technique,and their structures are fixed when circuits are designed,the self-adaptive ability is *** order to solve these problems,a novel circuit self-adaptive design technique based on evolvable hardware(EHW)is *** features robustness,self-organization and *** can be adapted to a complex environment through dynamic configuration of the *** this paper,the proposed technique *** consumption of hardware resources and the number of convergence iterations *** effectiveness and superiority of the proposed technique are *** designed circuit has the ability of resistible redundant-state interference(RRSI).The proposed technique has a broad application prospect,and it has great significance.

摘要：By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic （DTCTGAL） circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.

摘要：First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

摘要：A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnec- essary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.

摘要：By analyzing the principle of process variations, a lightweight Physical Unclonable Function （PUF） circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation （SMIC） 65 nm CMOS technology and the layout area is 2.94μm × 1.68μm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.

摘要：Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory （SRAM）,a design scheme of a novel ternary clocked adiabatic SRAM is *** scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary *** PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power *** with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.

摘要：We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology. An exhaustive algorithm is used to analyze the trade-off between area and speed of the global signal networks for this staggered buffer insertion scheme, and the criterion for determining the design parameters is presented. The comparative analytic result shows that the methods in this paper are proven to be more efficient for FPGAs with a large array size.

摘要：circuit design of 32 bit logarithmic skip adder (LSA) is introduced to implement high performance,low power *** carry lookahead adder is included into groups of carry skip adder and the hybrid structure costs 30% less hardware than *** circuit level,a carry incorporating structure to include the primary carry input in carry chain and an 'and xor' structure to implement final sum logic in 32 bit LSA are designed for better *** 5V,1μm process,32 bit LSA has a critical delay of 5 9ns and costs an area of 0 62mm 2,power consumption of 23mW at *** 2 5V,0 25μm process,critical delay of 0 8ns,power dissipation of 5 2mW at 100MHz is simulated.

摘要：A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2 μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.