摘要：综述了生物阻抗检测芯片的设计与优化,重点分析了双电极与四电极的适用场景及其在测量精度和便携性上的取舍。此外,针对不同检测需求,详细探讨了ADC法、dac法、逐次逼近法、半正弦dac法及基线消除技术的实现原理与特点。研究结果表明,双电极结合高效dac方法在便携设备中具有显著优势,而四电极配置则适用于高精度阻抗测量场景。本文为生物阻抗检测芯片的设计提供了理论支持,并展望了其在可穿戴医疗设备和动态监测领域的应用前景。

摘要：At present,the architecture of a digital-to-analog converter(dac) in essence is based on the weight current,and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase,which is 2^(n-1) times of its least weight *** for a dual weight resistance chain type dac,by using the weight voltage manner to D/A conversion,the D/A signal current is fixed to chain current I_(cha);it is only 1/2^(n-1) order of magnitude of the average signal current value of the weight current type *** principle is:n pairs dual weight resistances form a resistance chain,which ensures the constancy of the chain current;if digital signals control the total weight resistance from the output point to the zero potential point,that could directly control the total weight voltage of the output point,so that the digital signals directly turn into a sum of the weight voltage signals;thus the following goals are realized:(1) the total current is less than 200μA;(2) the total power consumption is less than 2 m W;(3) an 18-bit conversion can be realized by adopting a multi-grade structure;(4) the chip area is one order of magnitude smaller than the subsection current-steering type dac;(5) the error depends only on the error of the unit resistance,so it is smaller than the error of the subsection current-steering type dac; (6) the conversion time is only one action time of switch on or off,so its speed is not lower than the present dac.

摘要：A 500-MS/s 10-bit triple-channel current-steering dac in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The dac has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel dac occupies 0.5656 mm^2.

摘要：秉承同门Stellar Gain Cell dac设计精髓,造型简约,定价相对亲民的PS Audio(美诗)全新Stellar dac解码器,内置独门Digital Lens时钟重锁技术,有助化解寄生于数码信号内的毒素,令音色回复生动,重塑辽阔逼真临场感。3段式数码滤波,给予用家调校出个人喜好的音色,紧接的解码环节更选用ESS Technology技惊四座ES9018K2M Sabre Hyperstream晶片,缔造非比寻常的庞大动态。

摘要：A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit dac（digital-to-analog converter）.With this process,an NJFET with a pinch-off voltage ofabout-1.5 V and a breakdown voltage of about 16 V,an NLDDMOS（N-type lightly-dosed-drain in MOS） with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V,and a Zener diode with a reverse voltage of about 5.6 V were *** results showed that the converter had a reference temperature coefficient of less than±25 ppm/℃,a differential coefficient error of less than±0.3 LSB,and a linear error of less than±0.5 *** depletion-mode NJFET and its compatible process can also be widely used for high-voltage ADCs or dacs.

摘要：提出了一种基于晶体管电流源的1比特dac电路设计,电路由晶体管、电阻等分立器件构成,电路前端是FPGA将数字信息‘1’和‘0’编码为4路TTL电压脉冲,4路TTL电压脉冲分别控制4路晶体管电流源,然后将输出叠加为"阶梯"余弦信号,最后经过低通滤波得到适合基带传输的模拟信号,电路在ADS软件中仿真验证.

摘要：本文设计了一个数字输入和模拟输出呈斜锯齿波变化且位数可在７、１１、１５、１９位４种结果中选择的双ＤＡＣ电路。它设计在一单片机内，作掌型电脑的声音控制。

摘要：介绍一个12位的dac设计。它将整个12位分成两部分,低4位采用权重式电流元形式,高8位采用矩阵式电流元形式。这种方法可以广泛应用于各种dac的设计。

摘要：本文从硬件在回路系统（HITL）数字仿真的共性问题出发,以功能强大的计算机代数系统Mathematica为工具,提出了一种设计一般形式的dac数字补偿器的方法,以弥补工程上广为采用的信号重构器与理想滤波器在频率特性上的显著差异,减小误差。该方法简单、实用,物理意义直观、清晰。

摘要：设计了一种用于12位折叠插值ADC前台校准的高线性度dac。该dac包括电流源、开关电路、译码电路和电流-电压转换器。电流-电压转换器采用带共模反馈和增益提高技术的运放,具有高的共模抑制比和高的输出线性度。电流源的版图设计中考虑了电流源匹配特性,提出了"V"型布局方案,有效抑制其梯度误差和对称误差,提高了dac转换线性度。在TSMC 0.18μm CMOS工艺下对dac进行仿真。结果表明,当输入信号频率为4.101 5 MHz、采样频率为25MHz时,dac的有效位数达到7.97位。