摘要：This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.

摘要：In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a generic, robust and configurable Viterbi decoder with constraint length of 7, code rate of 1/2 and decoding depth of 36 symbols. The Viterbi decoder uses full-parallel structure to improve computational speed for the add-compare-select (ACS) modules, adopts optimal data storage mechanism to avoid overflow and employs three distributed RAM blocks to complete cyclic trace-back. It includes the core parts, for example, the state path measure computation, the preservation and transfer of the survivor path and trace-back decoding, etc. Compared to the general Viterbi decoder, this design can effectively decrease the 10% of chip logic elements, reduce 5% of power consumption, and increase the encoder and decoder working performance in the hardware implementation. Lastly, relevant simulation results using Verilog HDL language are verified based on a Xinlinx Virtex-II FPGA by ISE 7.1i. It is shown that the Viterbi decoder is capable of decoding (2, 1, 7) convolutional codes accurately with a throughput of 80 Mbps.

摘要：A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is *** on LDPC encoding theory,the FPGA-based coding algorithm is *** on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the *** addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder *** design scheme is implemented by FPGA hardware and verified by simulation and *** results show that the test results of the designed LDPC encoder are consistent with the theoretical ***,the coding system is practical,and the design method is simple and efficient.

摘要：MPEG4 XVIDencoder算法用SystemC加以实现,通过建立BitstreamCode、Motion、Texture、等并发模块,可以更加模块化地划分系统,在设计之初就可以对算法加以验证,通过行为级的建模,可以让系统的设计和模块划分更加适应硬件开发的流程,SystemC模型成为硬件模块的行为级参考,通过对每个模块的进一步细化就可以实现RTL编码,辅助硬件工程师完成从纯C代码到Verilog的跨越。

摘要：主要讨论基于IIS8 Web服务器下,采用IIS实时平滑流式处理技术设计了基于服务器/客户端模式的直播流媒体系统。详细介绍系统的配置过程,通过系统测试,验证了该流媒体直播系统根据客户端的带宽变化实时调整直播到客户端视频的质量。

摘要：视频处理机是基于TI的DSP TM320DM642芯片设计,高速信息处理性能,计算能力达4Gips使视频处理达到理想效果,可以做实时的视频采集,实现复杂的音视频压缩算法,带有以太网口,可以通过网络传输数据。主要应用于网络视频监控和其它复杂图象处理的高速DSP应用。