摘要：Using Technology Computer-Aided Design(TCAD) 3-D simulation,the single event effect(SEE) of 25 nm raised source-drain finfet is *** on the calibrated 3-D models by process simulation,it is found that the amount of charge collected increases linearly as the linear energy transfer(LET) increases for both n-type and p-type finfet hits,but the single event transient(SET) pulse width is not linear with the incidence LET and the increasing rate will gradually reduce as the LET *** impacts of wafer thickness on the charge collection are also analyzed,and it is shown that a larger thickness can bring about stronger charge *** reducing the wafer thickness could mitigate the SET effect for finfet technology.

摘要：An SOI MOSFET with finfet structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully *** can be well controlled by reducing fin *** performance can be achieved with thin height,so fin height is considered as a key parameter in device *** results show that finfets present performance superior to conventional single gate devices.

摘要：This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate finfet technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.

摘要：Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate finfet. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.

摘要：利用三维模拟软件Davinci对体硅finfet器件进行了详细的模拟。模拟结果显示体硅finfet器件能够有效的抑止短沟道效应,具有驱动电流大、散热好、成本低等优点。为了获得好的亚阈值特性,Fin的厚度要比较薄,同时Fin的高度不能太低,以保持足够的高度来抑止短沟道效应。沟道可以采用低掺杂或未掺杂设计,从而减少沟道内杂质对载流子的散射作用和杂质涨落效应对器件性能的影响。另外,为了获得合适的器件阈值电压,体硅finfet器件应当采用功函数在中间带隙附近的材料做栅电极,同时采用适当的功函数调节方法来获得合适的阈值电压。

摘要：信号电迁移的问题在先进工艺节点越来越受到重视。通过一个基于16 nm TSMC工艺的SoC芯片,分析了Innovus和Voltus两个工具在信号电迁移分析结果的差异。通过对成因的分析,解决了Innovus存在的问题,使得绝大多数信号电迁移问题在布局布线阶段得到解决,大大缩短了后端设计收敛时间。

摘要：基于finfet栅电容结构微观物理特性原理.通过能带结构关系推导了考虑量子效应的栅电容物理模型公式,使用TCAD搭建了finfet器件结构.通过MATLAB仿真出栅电容随栅电压变化的特性曲线,与理想状态对比得到在反型状态量子效应会使栅电容增大的结论,量子电容成为影响栅电容大小的主导因素,同时分析了不同状态下决定栅电容的因素.仿真了不同拟合参数对特性曲线的影响,为改善晶体管栅电容线性度的研究提供理论依据,提出的栅电容模型对基于finfet结构的电路设计研究具有了现实意义.

摘要：基于传统的束线离子注入在对finfet器件进行保形注入时面临的巨大挑战,介绍一种新的适用于finfet器件的掺杂技术,即等离子体浸没离子注入技术。总结了与束线离子注入技术相比,等离子体浸没离子注入技术在对finfet进行掺杂时的优点。利用自行设计并搭建的等离子体浸没超低能离子注入机分别对平面单晶硅和鳍状结构进行离子注入,并对鳍状结构进行快速退火。利用二次离子质谱(SIMS)测量了平面单晶硅的注入结深,通过透射电子显微镜(TEM)测试了退火前后鳍状结构的晶格损伤及修复状况,结果显示,利用等离子体浸没离子注入技术可以对鳍状结构进行有效的掺杂,而且对注入后的样片进行快速退火后,晶格损伤得到良好的修复。

摘要：上海2014年6月23日电/美通社/--电子设计自动化技术的领导厂商Mentor Graphics近日发布一份题为《finfet与多重图案拆分影响下的布局和布线》的研究报告。

摘要：finfet晶体管的兴起对IC物理设计和可测试性设计流程具有显著影响。引入finfet意味着在IC设计流程中，CMOS晶体管必须建模为三维（3D）器件，