摘要：A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with *** supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

摘要：This paper describes the design of a flexible Direct RF Sampling based GNSS receiver as well as its use for the verification of jitter effects on various performance metrics. The proposed architecture allows the sampling and the real-time digital signal processing of real GNSS signals. The analysis of the measurements obtained from this system validates theoretical formulations from which the sampling jitter limit is established in order not to impact the GNSS signal’s detection.

摘要：本文是参考RemyFourre发表在《StereoPhile》杂志上的文章翻译改写而成的。写这篇文章时，作者是UltraAnalog公司的副总裁。Fourre博士在法国出生并受教育，获得相当于美国计算机设计学士、电子学硕士、数学与机械博士、应用机械博士的学位。

摘要：A time-to-digital convener （TDC） oaseo on a reset-tree anti anti-harmonic oelay-locKeo oop （DLL） circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid ＂false locking＂. Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18μm CMOS technology, and its core area occupies 0.7 x 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than 4-0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.

摘要：我有个异想天开的问题：既然jitter是目前CD机靓声的大敌，能否设计一部内装大容量内存的机器，放入CD之后先将数码讯号读取在储存器内，这样既解决了jitter问题，还能消除震动对声音的影响，岂不一举两得?

摘要：笔者认为互动音乐的兴起,引领了中国音乐科技新时代的到来。文章介绍了互动音乐在中国的创作研究现状,总结出20世纪末至今互动音乐的三个发展阶段中,中国互动音乐作品的特征集中体现在以中国传统文化为创作主题,中国传统乐器的互动参与,创作呈现跨领域的合作趋势。经过从技术学习、模仿,到理念创新的过程,中国的互动音乐必然将从声音艺术的单一模式走向多媒体融合的艺术交互方式。

摘要：A sub-mA phase-locked loop fabricated in a 65nm standard digital CMOS process is presented. The impact of process variation is largely removed by a novel open-loop calibration that is performed only during start-up but is opened during normal operation. This method reduces calibration time significantly compared with its closed-loop counterpart. The dual-loop PLL architecture is adopted to achieve a process-independent damping factor and pole-zero separation. A new phase frequency detector embedded with a level shifter is introduced. Careful power partitioning is explored to minimize the noise coupling. The proposed PLL achieves 3. lps RMS jitter running at 1.6GHz while consuming only 0.94mA.

摘要：本文介绍了一种用于粒子物理实验的抗辐照高速并串转换电路芯片的设计,重点介绍了SOS抗辐照工艺,并串转换电路的结构。实现了一款基于SOS 0.25um工艺的8位5.12Gbps并串转换芯片,测试得到芯片的总晃动(total jitter)=53.20ps,其中随机晃动(random jitter)=1.84ps,确定性晃动(deterministic jitter)=33.93ps。

摘要：文章在仔细分析研究了RTP/RTCP实时传输协议的基础上,阐明了RTP/RTCP协议的基本原理。提出了一种嵌入式Linux平台下RTP/RTCP协议栈的设计模型与实现方案,并且详细论述了解决网络时延抖动的jitterBuffer机制。该设计与实现方案目前已应用于基于嵌入式Linux平台的媒体网关中,完全能够满足该媒体网关对于多路语音实时传输的通信需求。

摘要：High time-stability performance of the injection kicker system is important for the Beijing Electron Positron Collider Upgrade Project (BEPCⅡ),with jitter and drift less than±*** order to compensate the delay time drift of thyratron on the kicker pulsed power supply,a drift stabilizer is *** test results meet the demand of design by regulation resolution=1ns,jitter+drift<2ns in 8 *** detailed design of the time-drift stabilizer will be described in this paper.