摘要：A decomposition approach of the combinational functions is discussed. A design method, by which the minimization or near minimization of two-level combinational network can be obtained, is presented for a combinational function realized by using multiplexer universal logic modules. Using the method, the automated synthesis of the combinational functions can be accomplished on a computer.

摘要：There has been an increasing interest in integrating decision support systems (DSS) and expert systems (ES) to provide decision makers a more accessible, productive and domain-independent information and computing environment. This paper is aimed at designing a multiple expert systems integrated decision support system (MESIDSS) to enhance decision makers' ability in more complex cases. The basic framework, management system of multiple ESs, and functions of MESIDSS are presented. The applications of MESIDSS in large-scale decision making processes are discussed from the following aspects of problem decomposing, dynamic combination of multiple ESs, link of multiple bases and decision coordinating. Finally, a summary and some ideas for the future are presented.

摘要：An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits are de-signed by algebraic means. The design method based on this algebra may offer a design simpler than the previously knowll ones.

摘要：A practical approach is presented to enlarge the recoverable scope and improve the precision of pattern recovery. To specify both structural aspects and behavioral aspects of design patterns, we introduce traditional predicate logic combined with Alien's interval-based temporal logic as our theoretical foundation. Moreover, we take the Visitor pattern as an example to illustrate how to specify design patterns to support recovery of design patterns besides structural category. The experimental results show that the approach presented is practical for recovering design information of real world systems.

摘要：To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure hardware logic design. This paper outlines the principle of the scheme, blocks of logic design, and protocols design. The scheme provides higher downloading speed, wider flexibility on application, and improves work efficiency evidently. Key words： JTAGLink Debugger; Ethernet; FPGA; logic design