摘要：This article introduces an EEPROM memory cell model that is different from the equivalent capacitance model. This model uses high-frequency components in circuit design, including MOS transistors, zener diodes, resistors, capacitors, etc., and builds a model that can be used in most analog environments. The simulation of the transient process of write and read operations helps designers understand the working principle of EEPROM, and it can also be applied to the overall circuit design. According to the structure and working principle of the EEPROM cell device, a model of its equivalent circuit is established, and the read, write, and erase operations of the EEPROM cell are transiently simulated using this model. The simulation results verify the correctness of the model.

摘要：In the proposal, a construction project memory process based on the semantic annotation is presented. A project Mem-ory concerns the representation and the identification of the experience acquired during projects realization. The main feature of this approach is that the semantic annotation is used to build a continuous semantic design rationale process. We propose in this paper, a semantic traceability in four stages (identifying, structuring, annotating and integrating). The identification and the structuring phases use a model called Extended Marguerite model which fully considers the objectives of the project memory. The annotation phase exploits the results of precedent phase to prepare the final phase. Examples are presented from a case study in an Algerian firm called ENMTP. The architecture supporting the modelling engine is presented. Finally, an evaluation of the degree of the semantic annotation brought by proposed process is given.

摘要：随着系统芯片(SoC)上存储器比重的日趋增加和memory BIST(memory built-inself-test)的广泛应用,对较低测试功耗的嵌入式memory BIST的设计要求越来越高,因为测试功耗一般为系统正常工作时的两倍多,而过高的功耗会烧毁电路和降低芯片成品率.通过采用按时钟域划分存储器组和串并结合的方法来降低memory BIST的测试功耗.实验仿真结果表明,用该方法所得的最大功耗只有传统方法的1/14,可见该方法能有效降低测试时的能量损耗.

摘要：A DC-DC converter for flash memory IPs performing erasing by the FN (Fowler-Nordheim) tunneling and programming by the CHEI (channel hot electron injection) is designed in this paper. For the DC-DC converter for flash memory IPs using a dual voltage of VDD (=1.5V±0.15V)/VRD (=3.1V±0.1V), a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD (=3.1V±0.1V) is a regulated voltage by a voltage regulator with an external voltage of 5V, which is used as the WL activation voltage in the read mode and an input voltage of the charge pump. The designed DC-DC converter outputs positive voltages of VP6V (=6V), VP8V (=8V) and VP9V(=9V);and a negative voltage of? VM8V (=-8V) in the write mode.

摘要：对于memory的研究,大部分都只是停留在对容量的扩充,速度的提高等性能提升方面,很少涉及对memory进行辅助设计以实现更多的特殊功能.提出了一种通过对memory地址作用加解密算法,利用memory自身的特性来实现对数据的加解密的功能,并通过实验仿真验证了该方法的可行性.

摘要：历史上的11月3日，有着很多珍贵的纪念。面对于人气组合岚而言，10年之后的这一天，也是他们迎来出道纪念的特殊见证。见证一个曾经毫不起眼的组合在10年的时间里，从青涩走向成熟，也从平凡走向了荣耀。

摘要：1 DDR总线的设计、调试和验证在计算机架构中,DDR作为程序运算的动态存储器,面对如高性能计算、图形计算、移动计算、工业应用等领域的要求,发展出DDR4,以及用于图形计算的GDDR5,HBM2,面向移动计算的低功耗LPDDR4等标准。处理器的运算速度越来越快,DDR的性能也要求越来越高,明显的趋势是DDR总线工作频率持续提升,DDR4达到3.2 GT/s.

摘要：本文介绍了一种新的Flash memory快闪存储器的设计方法,运用该方法可以有效地提高串型接口NOR Flash memory读取数据的频率。这种设计方法采用对memory存储器中的寄生电容用输入地址进行控制,使其在不同的时间段进行充电,达到Flash memory读取数据所需的电压可以在很短的时间内达到读取数据所要求满足的电压的目的,从而提高了存储器数据读取的速度。同时此设计方法取消了数据读取过程中不必要的对寄生电容的充电和放电过程,降低了对电源的功耗,有效提升产品的竞争力。

摘要：本文介绍了memory Pool的历史、设计思想及其在C++中的实现。读者基础:有一定程度的C++编程经验本文适用工具:GNU C++编译器本文关于SGI STL之剖析,部分已载于《STL源码剖析》第二章;崭新内容包括SGI STL区块卸除(归还)动作分析、缺点与补强之道、无痛应用、三种编译器之区块配置效能比较。

摘要：本文介绍了单管存储(Fiash memory)单元的优点、单元结构及工作原理。