摘要：We design a reconfigurable pipelined multiplier embedded in an FPGA. This design is based on the modified Booth algorithm and performs 18 × 18 signed or 17 × 17 unsigned multiplication. We propose a novel method for circuit optimization to reduce the number of partial products. A new layout floorplan design of the multiplier block is reported to comply with the constraints imposed by the tile-based FPGA chip design. The multiplier can be configured as synchronous or asynchronous. Its operation can also be configured as pipelined for high-frequency operation. This design can be easily extended for different input and output bit-widths. We employ a novel carry look-ahead adder circuit to generate the final product. The transmission-gate logic is used for the low-level circuits throughout the entire multiplier for fast logic operations. The design of the multiplier block is based on SMIC 0.13μm CMOS technology using full-custom design methodology. The operation of the 18 × 18 multiplier takes 4. lns. The two-stage pipelined operation cycle is 2.5ns. This is 29.1% faster than the commercial multiplier and is 17.5% faster than the multipliers reported in other academic designs. Compared with the distributed LUT-based multiplier,it demonstrates an area efficiency ratio of 33 ： 1.

摘要：This paper presents a new kind of macromodel of OTA,which can be used to solve the problem in which the two port macromodel couldnt reflect some functions of the *** new model also opens up a new way for the simulation of the OTA *** paper discusses the way of designing this model and simulating it in *** result proves its reasonable design and its simplicity in *** the application of this model,we design a complete symmetric double differential quarter square OTA multiplying unit by using four three port OTA *** successfully solved the problem of the unsymmetry of two input ports in an OTA multiplying *** result fully agrees with the experiment.

摘要：In today’s digital era, developing digital circuits is bounded by the research towards investigating various nano devices. This paper provides the design of compact Baugh-Wooley multiplier using reversible logic. Even though various researches have been done for designing reversible multiplier, this work is the first in the literature to use Baugh-Wooley algorithm using reversible logic. In this work, a new 5 × 5 reversible multiplier cell is proposed which will be useful in designing Baugh-Wooley multiplier. The proposed single multiplier cell is able to perform addition of a 1 × 1 product with the sum and carry from the previous cell. This reversible multiplier cell is useful in building up regularity in the array multipliers. The Toffoli gate synthesis of the proposed reversible multiplier cell is also given.

摘要：Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges *** leakage currents,the short-effect channel,and high energy dissipation are some of the ***-dot cellular automata(QCA)represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard *** key point of designing arithmetic circuits is based on the structure of a 1-bit full adder.A low-complexity full adder block is beneficial for developing various intricate *** paper represents scalable 1-bit QCA full adder structures based on cell *** proposed full adders encompass preference aspects of QCA design,such as a low number of cells used,low latency,and small area ***,the proposed structures have been expanded to larger circuits,including a 4-bit ripple carry adder(RCA),a 4-bit ripple borrow subtractor(RBS),an add/sub circuit,and a 2-bit array *** designs were simulated and verified using QCA Designer-E version *** tool can estimate the energy dissipation as well as evaluate the performance of the *** results showed that the proposed designs are efficient in complexity,area,latency,cost,and energy dissipation.

摘要：This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.

摘要：Y2002-63119-657 0218715使区域延迟积最小的限于2扇形最佳对数加法器结构=Optimal logarithmic adder structures with a fanout oftwo for minimizing the area-delay product [会,英]/Ziegler, M. & Stan, M.//The IEEE InternationalSymposium on Circuits and Systems Vol. 2 of 5. —657～660(HE)