摘要：At Physikalisch-Technische Bundesanstalt (PTB), superconducting 10 V circuits for the programmable Josephson voltage standard (PJVS) are routinely manufactured on the basis of NbxSi1-x barrier junctions. This paper describes in detail the basic design principles for an operating frequency of 70 GHz. It starts with single junctions, discusses their insertion into microstriplines and closes with the whole microwave circuit containing 69,632 NbxSi1-x barrier junctions arranged over 128 microstriplines connected in parallel. The microwave attenuation of this junction type is a key parameter for the 10 V design and we report its experimental determination. Special attention has been devoted to subarrays with just a few Josephson junctions in one of the outermost striplines. The arrangement of these subarrays determines the optimum performance of the complete 10 V series array. The high performance of programmable 10 V circuits fabricated at PTB is characterized by measured operating margins in all subarrays of more than 1 mA centered at the same dc bias current. The observed modulation of the current margins, when changing the frequency around 70 GHz, is explained by microwave reflections caused by the rf waveguide inside the cryoprobe. We determine the current margins in dependence of the output power of a microwave synthesizer and show that 60 mW is sufficient to achieve current margins larger than 1 mA.

摘要：A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

摘要：赛灵思公司(Xilinx)日前宣布将举办programmable World 2004技术论坛，这是一系列深度技术专题研讨会，着重介绍设计实例以及在新一代可编程系统设计中发挥重要作用的新产品。公司计划于11月9日～18日在亚太地区的4个城市分别举行为期一天的活动，展示其突破性的Virtex-4平台解决方案，并举办全天的技术会议，对每一数字领域进行专门的讨论，包括DSP、嵌入式处理、连接功能和逻辑。

摘要：The Hefei Light Source-Ⅱ(HLS-Ⅱ) is a vacuum ultraviolet synchrotron light source. The personnel safety system (PSS), which is a personnel access control system, is a crucial part of the HLS-Ⅱ, as it protects the staff and users at HLS-Ⅱfrom radiation damages. The prior version of HLS-Ⅱ PSS was based on an access control system called SiPass. This lacked the personnel management function. Meanwhile, as the prior PSS is a turn-key system, it was not effective for sharing information. To overcome these drawbacks, the novel design of PSS for HLS-Ⅱ is proposed based on the Siemens redundant programmable logic controller under the Experimental Physics and Industrial Control System. The proposed PSS consists of a safety interlock system, access control system, and a radiation monitoring system. The safety interlock system is used to define the interlock logic. The access control system is designed to restrict the access of staff and users at HLS-Ⅱ, and to provide a personnel management function. The radiation monitoring system is used to monitor the radiation dose rate in both the light source and the surrounding areas. This paper details the architecture and the specific design of the novel PSS. The off-line test results demonstrate that the proposed system has achieved the design objectives.

摘要：空间太阳望远镜太阳磁场测量要求图象的信噪比为104.受CCD满阱电荷的限制,必须对CCD采集到的图象,在预处理单元进行图象积分以提高信噪比;为了减小CCD引入的噪声,还采用了CCD图象改正技术;对于宁静态的长时间太阳观测,为了克服图象漂移导致无法进行图象积分的难题,提出了图象相关内插累加技术,来进一步提高信噪比;预处理单元还担负着偏振测量中的Stokes参数归一计算、CCD控制、调焦控制和图象格式化等任务.文中分析了预处理系统的处理功能需求,确定了系统设计方案;采用FPGA加DSP的硬件结构,制作了地面原理样机,开发了系统软件.在地面支持设备上对系统功能进行了仿真和测试.

摘要：为了构建一套数字化核测量系统,设计并实现了一种适用于阻容反馈式和开关复位式核探测器的前端控制器。导出了辐射计数率n、输入信号幅度Vin、后续ADC变换量程?V及线性放大倍数A之间的数量关系;通过CPLD(Complex programmable Logic Device)对数字电位器的控制来实现增益的分段调节;通过碲锌镉探测器的不同增益下的测量实验验证了设计的可行性。

摘要：An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

摘要：This paper addresses the challenges of System-on-Chip designs using High-Level Synthesis (HLS). HLS tools convert algorithms designed in C into hardware modules. This approach is a practical choice for developing complex applications. Nevertheless, certain hardware considerations are required when writing C applications for HLS tools. Hence, in order to demonstrate the fundamental hardware design concepts, a case studyis presented. Fast Fourier Transform (FFT) implementation in ANSI C is examined in order to explore the important design issues such as concurrency, data recurrences and memory accesses that need to be resolved before generating the hardware using HLS tools. There are additional language constraints that need to be addressed including use of pointers, recursion and floating point types.

摘要：针对工程实践中造纸机PLC控制程序存在设计效率低、通用性不强等特点,提出运用软件工程方法对其进行标准化设计。通过分析造纸机多分部传动控制的特点,采用结构化方法进行需求分析和程序设计。实践验证,该方法应用在造纸机上是可行的,且能提高程序的设计效率和通用性。软件工程的软件设计方法在工业控制领域的应用具有很好的前景。

摘要：可编程逻辑器件(programmable Logic Device,简称PLD)是20世纪70年代发展起来的一种新型逻辑器件,它是现代数字电子系统向超高集成度、超低功耗、超小型封装和专用化方向发展的重要基础。它的应用和发展不仅简化了电路设计,降低了成本,提高了系统的可靠性和保密性,而且给数字系统的设计方法带来了革命性的变化。CPLD(Complex programmable Logic Device),即复杂可编程逻辑器件,它是20世纪90年代初期出现的EPLD改进器件。同EPLD相比,CPLD增加了内部连线,对逻辑宏单元和I/O单元也有重大的改进。Xilinx是世界上最大的可编程逻辑器件供应商之一,FPGA的发明者。产品种类较全,主要有:XC9500/4000,Coolrunner(XPLA3),Spartan,Vertex。在本文中,我们将通过对CPLD的发展、结构、应用和设计等方面的认知,了解CPLD的基本原理,并设计出CPLD脱机编程写入器的电路图。