摘要：In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.

摘要：This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity

摘要：The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET system which can easily design the timing control. Each channel consists of a charge preamplifier, slow/fast shaper, discriminator and an analog memory. There are an ADC and a TDC to process the energy information and time information for each channel at the same time. In this paper, the whole system signals flow is all simulated by MATLAB. The simulation results show that the proposed system can process slender current from the detector and achieve the energy and time information. The proposed architecture can be applied to high-resolution PET imaging systems with multi-channel ASICs.

摘要：In this paper, we present an ultrafast digitizer utilizing the DRS4 switched capacitor array applicationspecific integrated circuit to achieve an ultrafast sampling speed of at most 5 GS/s. We cascaded all eight channels(sub-channels) of a single DRS4 chip for increased storage depth. The digitizer contains four DRS4 chips, a quadchannel analog-to-digital converter,a controlling fieldprogrammable gate array, a PXI interface, and an SFP+connector. Consequently, each DRS4 channel has a depth of 8192 points and a vertical resolution of 14 bits. The readout sequences should be broken into several segments and then reordered to obtain the correct sequential data sets, and this offline procedure varies in different readout modes. This paper describes the design and implementation of the hardware;in particular, the respective processing procedures are described in detail. Furthermore, the offset error is calibrated and corrected to improve the precision of the captured waveform in both single-channel and highresolution modes.

摘要：本文介绍了BESⅢ Muon前端电子学读出系统的结构,详细说明了依据菊花链方式的前端板和基于USB的读出板的设计和实现方法。该系统中较多地采用了FPGA技术,极大地降低了系统的复杂程度和建造成本。文章最后介绍了系统的自检方式,并给出了该系统在北京高能物理研究所谱仪大厅内的宇宙线测试结果,论证了系统的可靠性。