摘要：A reconfigurable dual-band LNA is presented. The LNA employs switching capacitors and circuit in to realize the dual-band operation. These methodologies are used to design and implement a reconfigurable LNA for IMT-A and UWB application. The LNA is implemented using TSMC-0.13 μm CMOS technology. Measured performance shows an input matching of better than -13.5 dB, a voltage gain of 18-22.8 dB, with an NF of 4.3-4.7 dB in the band of 3.4-3.6 GHz, and an input matching of better than -9.7 dB, a voltage gain of 14.7-22.4 dB, and with an NF of 3.7-4.9 dB in the band of 4.2-4.8 GHz. According to the measure results, the proposed LNA achieves dual-band operation, and it proves the feasibility of the proposed topology.

摘要：Efficient reconfigurable field programmable gate array （FPGA） architectures for the MD6-224/256/384/512 Hash algorithm are proposed in this article. The basic iterative compact design requires 923 ALMs and achieves a throughput ranging from 225 Mbit/s to 394 Mbit/s at a maximum frequency of 198 MHz. The 32-step-urtrolled high-throughput design requires 7 090 ALMs and achieves a throughput ranges from 5 776 Mbit/s to 9 490 Mbit/s at a maximum frequency of 173 MHz. The simulation results show that high flexibility and efficient FPGA implementation of the MD6 Hash function is achieved.

摘要：reconfigurable mechanisms can deliberately reconfigure themselves by rearranging the connectivity of components to meet the different requirements of *** and origami-derived mechanisms are two kinds of typical reconfigurable mechanisms,which have attracted increasing attention in the field of mechanisms since they were *** the in dependent design level,innovation,and international competitive powers of reconfigurable mechanical products is *** related significant innovation research and application achievements periodically will shed light on research directions and promote academic *** paper presents an overview of recent developments in innovation design of reconfigurable mechanisms in China,including metamorphic and origami mechanisms and their typical *** future development trends are analyzed and forecasted.

摘要：The composite field multiplication is an important and complex module in symmetric cipher algorithms, and its realization performance directly restricts the processing speed of symmetric cipher algorithms. Based on the characteristics of composite field multiplication in symmetric cipher algorithms and the realization principle of its reconfigurable architectures, this paper describes the reconfigurable composite field multiplication over GF（（2^8）k） （k=1,2,3,4） in RISC （reduced instruction set computer） processor and VLIW （very long instruction word） processor architecture, respectively. Through configuration, the architectures can realize the composite field multiplication over GF（2^8）, GF （（2^8）2）, GF（（28）3） and GF（（28）4） flexibly and efficiently. We simulated the function of circuits and synthesized the reconfigurable design based on the 0.18 μm CMOS （complementary metal oxide semiconductor） standard cell library and the comparison with other same kind designs. The result shows that the reconfigurable design proposed in the paper can provide higher efficiency under the premise of flexibility.

摘要：In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.

摘要：Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.

摘要：We design a reconfigurable pipelined multiplier embedded in an FPGA. This design is based on the modified Booth algorithm and performs 18 × 18 signed or 17 × 17 unsigned multiplication. We propose a novel method for circuit optimization to reduce the number of partial products. A new layout floorplan design of the multiplier block is reported to comply with the constraints imposed by the tile-based FPGA chip design. The multiplier can be configured as synchronous or asynchronous. Its operation can also be configured as pipelined for high-frequency operation. This design can be easily extended for different input and output bit-widths. We employ a novel carry look-ahead adder circuit to generate the final product. The transmission-gate logic is used for the low-level circuits throughout the entire multiplier for fast logic operations. The design of the multiplier block is based on SMIC 0.13μm CMOS technology using full-custom design methodology. The operation of the 18 × 18 multiplier takes 4. lns. The two-stage pipelined operation cycle is 2.5ns. This is 29.1% faster than the commercial multiplier and is 17.5% faster than the multipliers reported in other academic designs. Compared with the distributed LUT-based multiplier,it demonstrates an area efficiency ratio of 33 ： 1.

摘要：This paper presents a modification of an existing cognitive antenna design which contains two antennas: one is a sensing that covers the band from 1 - 11 GHz and the other is a hybrid triangular reconfigurable antenna. Two antennas are combined together to create a new design which called Cognitive Antenna. The new shape of the reconfigurable antenna will affect the cognitive antenna so as to work at two different frequencies via rotation by 180°. At each rotation, the antenna takes single frequency from number of possible frequencies that sensing antenna would find.

摘要：In this paper we present the design and prototyping of an arithmetic processor based on reconfigurable technology, whose purpose is to determine in a parallel manner the quality of the solution in a radio network design optimization problem. This problem consists in the search for an optimal set of locations in which to place radio antennas in order to obtain the maximum possible coverage, for a given terrain and antenna characteristics. The original computational contribution of this work is to use programmable logic devices to avoid the high cost of computing the evolutionary algorithms required to tackle this optimization problem. This is achieved by means of reconfigurable processors working in parallel. On the basis of the results obtained from the prototype, it may be considered a parallel architecture capable of achieving a great acceleration in the calculations.

摘要：针对SoPC系统远程实时更新的实际需要,设计并实现了一种基于Virtex-ⅡPro XC2VP30平台的在线动态可重构SoPC系统。该系统应用IRL设计理念和局部动态重构技术,利用Xilinx公司的ISE8.2、EDK8.2、PlanAhead10.1和SystemGen-erator10.1等开发工具,对算术运算和音频处理模块进行局部动态重构和远程实时更新。经实验结果表明,该系统能够通过局部动态重构技术使电路重构的时间缩短到1s左右,还能够完成配置文件的远程在线实时更新,适用于地理位置较偏远、对安全性要求较高的场合。