摘要：A 1200-V thin-silicon-layer p-channel silicon-on-insulator(soi)lateral double-diffused metal-oxide-semiconductor(LDMOS)transistor is *** device named INI soi p-LDMOS is characterized by a series of equidistant high concentration n+islands inserted at the interface of a top silicon layer and a buried oxide ***−mode holes,caused by the electric potential dispersion between the device surface and the substrate,are located in the spacing between two neighboring n+islands,and greatly enhance the electric field of the buried oxide layer and therefore,effectively increase the device breakdown *** on a 2−µm−thick buried oxide layer and a 1.5-µm−thick top silicon layer,a breakdown voltage of 1224 V is obtained,resulting in the high electric field(608 V/µm)of the buried oxide layer.

摘要：In this paper, the multimode waveguide lengths and the output port locations of a soi （silicon on insulator） material-based 1×4 MMI （multimode interference） optical splitter are optimized by means of FD-BPM （finite difference - beam propagation method）. An improved 1×4 MMI optical splitter is designed. Compared with an usual optical splitter, a smaller loss 0. 12dB and a better output port power uniformity 0.11dB are achieved for the optical signal transmission.

摘要：The design method for a high-voltage soi trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage （BV） and specific on-resistance （Rs, on） into account. The high-k （relative permittivity） dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An soi LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs, on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.

摘要：将soi技术优势引入SiGe HBT,可满足当前BiCMOS高速低功耗的应用需求.soi SiGe HBT作为BiCMOS工艺的核心器件,其频率特性决定了电路所能达到的工作速度.为此,本文针对所提出的soi SiGe HBT器件结构,重点研究了该器件的频率特性,并通过所建立的集电区电容模型予以分析.规律和结果为:1)soi SiGe HBT特征频率随集电区掺杂浓度的升高而增加;2)soi SiGe HBT特征频率与集电极电流IC之间的变化规律与传统SiGe HBT的相一致;3)正常工作状态,soi SiGe HBT(集电区3×1017cm-3掺杂)最高振荡频率fmax大于140 GHz,且特征频率fT大于60 GHz.与传统SiGe HBT相比,特征频率最大值提高了18.84%.以上规律及结论可为soi SiGe HBT及BiCMOS的研究设计提供重要依据.

摘要：在Ｄａｉｓｙ系统上设计出通用性强、使用方便的ＳＯＩ门阵列母版及门阵列电路，并采用１．５μｍＣＭＯＳ／ＳＯＩ工艺在薄膜全耗尽ＳＩＭＯＸ材料上得以实现，其中包括多种分频器电路和环形振荡器，环振可工作在２．５Ｖ，门延迟时间在５Ｖ时为４３０ｐｓ。

摘要：给出了soi近红外Si0.8Ge0.2/Si横向pin光电探测器的设计和制作过程。对制得的样管进行了典型光电参数的测试。测试结果表明,探测器的响应波长范围为0.4～1.3μm,峰值响应波长在0.93～0.97μm,峰值波长下响应度达0.38μA/μW,与Si光电探测器相比,出现明显的响应波长范围和响应峰值波长红移,光电性能达到了预先的设计目标。

摘要：提出一种soi基背栅体内场降低BGREBULF(back-gate reduced BULkfield)耐压技术.其机理是背栅电压诱生界面电荷,调制有源区电场分布,降低体内漏端电场,提高体内源端电场,从而突破习用结构的纵向耐压限制,提高器件的击穿电压.借助二维数值仿真,分析背栅效应对厚膜高压soi LDMOS(>600V)击穿特性的影响,在背栅电压为330V时,实现器件击穿电压1020V,较习用结构提高47.83%.该技术的提出,为600V以上级soi基高压功率器件和高压集成电路的实现提供了一种新的设计思路.

摘要：提出了一种基于soi材料的新型3×3多模干涉(MMI)波导光开关,在开关的多模波导中引入折射率调制区,利用硅的等离子色散效应改变多模波导局部区域的折射率,使得光场在传输过程中的相位发生变化,进而确定输出光场位置,实现开关功能。采用有限差分光束传播法(FD-BPM)方法对开关的各个状态进行了模拟和分析,并对器件的结构参量进行了优化设计,采用优化后的结构参量,开关可实现的最大消光比达到-17.27 dB。

摘要：在超紧缩双曲锥形 3dB多模干涉耦合器的基础上 ,设计了一种新的Silicon on insulator(soi)Mach Zehnder干涉型电光调制器 与传统的Y分支器相比 ,双曲锥形 3dB耦合器的制作容差大 ,而长度缩短了近 30 % ,使得整个器件的尺寸大幅减小 调制区采用横向注入的PIN结构 ,模拟结果表明 :当外加偏压为 0 .86V时 ,器件的调制深度最大 ,此时注入电流为 13.2mA ,对应的器件功耗为 11.

摘要：根据受抑全反射的光学隧道效应和Ｇｏｏｓ－ｈａｎｃｈｅｎ位移分析ＳＯＩ全内反射型光波导开关中导模的传输和反射特性。在讨论等离子体戏散效应，ｐ－ｎ结大注入效应的基础上，分析了全内反射光波导开关的电学性质。设计了该器件的结构参数和电学参数。