摘要：With more scaling, the speed of than 40 years Moore CMOS transistors is around 100 GHz. Such fact makes it possible to realize mm-wave circuits in CMOS. However, with the target of achieving broadband and power-efficient operation, 60 GHz CMOS RF transceiver faces severe challenges. After reviewing the technology issues, regarding the 60 GHz applications, this paper discusses design challenges both from the system and the building block levels, and also presents some simulated or measured circuits results.

摘要：Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.

摘要：Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency （RF） application-specific integrated circuit transceiver tbr Human Body Commnunication （HBC） is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying （OOK）/Frequency-Shift Keying （FSK） modulation protocol and an OOK/FSK delrodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70%. A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addi-tion, a low power autonmatic-gain-control system is realized using a novel architecture, thereby render-ing the peak detector circuit and loop filter unneces-sary. Finally, the complete chip is fabricated. Simula-tion results suggest receiver sensitivity to be-75 dBm. The transceiver shows an overall power con-smxption of 32 mW when data rate is 5 Mbps, de-livering a P1dB output power of - 30 dBm.

摘要：Designing low power sensor networks has been the general goal of design engineers, scientist and end users. It is desired to have a wireless sensor network (WSN) that will run on little power (if possible, none at all) thereby saving cost, and the inconveniences of having to replace batteries in some difficult to access areas of usage. Previous researches on WSN energy models have focused less on the aggregate transceiver energy consumption models as compared to studies on other components of the node, hence a large portion of energy in a WSN still get depleted through data transmission. By studying the energy consumption map of the transceiver of a WSN node in different states and within state transitions, we propose in this paper the energy consumption model of the transceiver unit of a typical sensor node and the transceiver design parameters that significantly influences this energy consumption. The contribution of this paper is an innovative energy consumption model based on simple finite automata which reveals the relationship between the aggregate energy consumption and important power parameters that characterize the energy consumption map of the transceiver in a WSN;an ideal tool to design low power WSN.

摘要：Authors designed an obstacle radar transceiver for ISM band. This work is focused on rectangular microstrip transceiver integrated with innovative metamaterial structure at a height of 3.276 mm from the ground plane. Two rectangular microstrip transceiver is designed for transmitting and receiving purpose. This work is mainly focused on increasing the potential parameters of rectangular microstrip transceiver. RMT along with the proposed innovative metamaterial structure is designed to resonate at 2.259 GHz. Simulation results showed that the impedance bandwidth of the RMT is improved by 575%, return loss is reduced by 391% and efficiency is improved by 28% by incorporating the proposed innovative metamaterial structure. For verifying that the proposed innovative metamaterial structure possesses negative values of Permeability and Permittivity within the operating frequency range, Nicolson-Ross-Weir method (NRW) has been employed. An op-amp and comparator is used to compare the return loss of transmitting and receiving RMT. An indicator is used to indicate difference of return loss and power of transmitting and receiving rectangular microstrip transceiver. For all simulation purpose, computer simulation technology-microwave studio (CST-MWS) software has been used.

摘要：在是否刊登此文时编辑有些犹豫，transceiver是一个商品软件，发这篇文章是否有作广告之嫌，但仔细阅读，排除那些类似产品说明书的文字，作者还是剖析了这个软件的总体结构，并介绍了具体的应用开发代码，对于Delphi开发设计者非常有用，读者可以看到一个具体产品的设计与应用实例，在实际工作中可以借鉴其设计思想与方法。

摘要：The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.

摘要：A monolithic LC-tuned voltage controlled oscillator （LC-VCO） with 2 tuning terminals is designed for a dual frequency conversion transceiver for WLAN and realized using 0.18μm radio frequency （RF） CMOS technology. The output frequency range can be tuned to cover the defined frequency band of the transceiver. The maximum tuning range is 500MHz. The phase noises are - 117dBc/Hz at 4MHz and - 107dBc/Hz at 500kHz,both off the center frequency of 4. 189GHz. The RMS-jitter of the output signal is 4. 423ps,and the output power is - 8. 68dBm.

摘要：随着航天测控技术的飞速发展,系统传输速率成为了限制系统整体性能的关键因素之一。Serdes接口以其传输速率高、抗干扰能力强、功耗低等优点,迅速成为高速传输接口发展的主流。针对串行链路速率及带宽不断提高的问题,提出了一种基于Arria10 FPGA芯片的高速Serdes接口模块的设计方案。通过板间的高速数据传输实验,使用transceiver Toolkit验证了经过PMA参数优化后的单路10 Gbps的传输速率以及最高768 Gbps的总传输带宽,解决了高速传输系统对传输带宽要求高的问题,为系统实现高速数字开关矩阵的设计提供了技术支持。