摘要：A modified extended binary Euclid's algorithm which is more regularly iterative for computing an inversion in GF(2m) is presented. Based on above modified algorithm, a serial-in serial-out architecture is proposed. It has area complexity of O(m), latency of 5m-2, and throughput of 1/m. Compared with other serial systolic architectures, the proposed one has the smallest area complexity, shorter latency. It is highly regular, modular, and thus well suited for high-speed VLSI design.