摘要：To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is *** is achieved by operating the current mirrors and the output current of the operational transconductance *** the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage *** charge pump small-signal model is used to describe the device’s dynamic behavior and *** predictions were verified by Hspice simulation and *** driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 *** output response time is less than 8μs,and the load current jumps from 400 to 800 mA.

摘要：A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage ***,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of *** results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μ*** average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

摘要：A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

摘要：To meet the demands for different supply voltage levels on SOC required by digital modules like CPU core and analog modules,a novel dual-output charge pump is proposed. The charge pump can output a step-up and a step-down voltage simultaneously with a high driving capability. The multiple gain pair technique was introduced to enhance its efficiency. The proposed co-use technology for capacitors and switch arrays reduced its cost. The charge pump was designed and fabricated in a TSMC 0.35μm mixed-signal CMOS process. A group of analytical equations were derived to model its static characteristics. A state-space model was derived to describe its small-signal dynamic behavior. Analytical predictions were verified by Spectre simulation and testing. The consistency of simulated results as well as test results with analytical predictions demonstrated the high precision of the derived analytical equations and the developed models.

摘要：An improved charge-averaging charge pump and the corresponding circuit implementation are presented. The charge-averaging charge pump proposed by Koo is analyzed and a new scheme is proposed. This new scheme decreases power by 1/3 and eliminates the practical defects in the original. Spectre Verilog behavioral simulation results show that the proposed scheme can strongly reduce the energy of spurs. Circuit implementation of this new charge pump for a frequency synthesizer with a fractional division ratio of 1/3 is then presented and multi-level simulation is performed to validate its feasibility at the circuit level. The simulation results show this new scheme outputs a flat voltage curve in a locked state and can thus effectively suppress fraction spurs.

摘要：A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.

摘要：A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.

摘要：A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

摘要：This paper presents an integrated power management unit （PMU） for a battery-operated wireless endoscopic system. This PMU is integrated with a baseband chip in standard 0.18μm CMOS technology,promising low cost, ease in PCB design, and a minimum in system size. The optimized power supply architecture is derived from comparison. Circuits of sub blocks are presented in detail. As a result, only five small off-chip capacitances are required by PMU with an overall quiet current consumption of less than 100μA. Moreover,a digital calibration method is adopted to alleviate the effect of process variation. The achieved performance is also demonstrated with corresponding measurement results.

摘要：An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.