摘要：A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-n synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.

摘要：A wideband fractional-n frequency synthesizer is implemented in a 65 nm CMOS *** employs a wideband LC voltage-controlled oscillator（VCO） with optimized VCO gain（KVCO/and a sub-band step to improve automatic frequency calibration（AFC） efficiency at negligible expense of phase noise *** agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth *** results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant *** frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.

摘要：A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-n phase-locked loop（PLL）is adopted in the *** transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.