摘要：基于分光法的晶体阵列解码技术是正电子发射成像系统最为高效的探测器设计方案之一,但目前基于分光法的晶体阵列解码设计依赖于经验和实验迭代,晶体解码和分光层设计缺少有效的仿真方法。该文采用了gate仿真软件,对分光法的探测器进行建模仿真,提出了逐列逼近的优化算法对分光层反光片进行长度优化设计,且对优化仿真中主要参数进行了分析,并组装4mm×4mm×25mm、12×12阵列实验模块对所提方法进行验证。实验结果表明:该基于gate仿真的优化设计方法能有效实现分光法探测器晶体阵列解码的仿真以及解码斑点均匀分布的反光片长度优化设计。

摘要：采用基于Mont Carlo方法的gate软件包,设计了GE Discovery LS型PET系统的仿真模型。在此基础上,依据Discovery LS的探测环几何,在ROOT环境下进行了相关辅助工具的开发,实现了gate列表格式原始符合数据到Interfile3.3格式正弦图数据的离线转换,从而完成仿真平台各环节间的数据接口。以原型系统的实验测试数据为参考,通过仿真分析初步确认了所构建仿真系统的近似度与有效性。结果表明,仿真数据与实验数据能够较好地吻合,真实系统的主要特性在核医学仿真平台中得到了再现。

摘要：正电子发射断层成像PET(Positron Emission Tomography)是一套庞大、复杂而又极其精密的大型医疗设备,由成千上万个探测单元及相应的信号采集通道组成,其复杂的采集逻辑直接导致系统前期研发迭代次数多、硬件调试困难,且时间与资金成本投入高。本文通过研究PET系统整体结构及前端电子采集模块的功能,设计出基于gate仿真软件(Geant4 application for tomographic emission)和MATLAB(matrixlaboratory,Mathworks Inc.)数据处理包的PET电子学仿真架构,利用数字化单事件重建DiSER(digitalsingle-event-reconstruction)模型将gate仿真得到的湮灭事件的能量、时间信息进行综合,转换为光子脉冲信号并由模数转换器ADC(analog-to-digital converter)进行量化,量化数据输入到现场可编程门阵列FPGA(field programmable gate array)和MATLAB协仿真模块中,验证FPGA硬件采集算法的可行性。待各模块的湮灭事件采集完毕,将多模块数据进一步综合输入到FPGA符合处理模块中,完成PET系统符合单元的功能验证。最后,将设计的算法在基于飞行时间技术的TOF(time-of flight)-PET样机上进行了测试,验证了设计的有效性和正确性。该系统仿真平台可应用于PET系统整个研发周期,其搭建思路也可灵活、有效地拓展到其他领域的系统建模与验证之中。

摘要：为研究运动发酵单胞菌合成生物学及代谢工程,评估运动发酵单胞菌内源启动子及终止子,需要建立一种方便有效的多基因代谢途径组装方法.通过Golden gate方法构建了一个含有运动发酵单胞菌乙醇脱氢酶2编码基因启动子区(P_(adh2))、丙酮酸脱羧酶编码基因终止子区(T_(pdc))和绿色荧光蛋白开放阅读框(gfp)的人工转录单元.将含有IIS型限制内切酶Bbs I识别和酶切序列的特异性接头添加到P_(adh2)、T_(pdc)和gfp序列两侧,从而保证在一个反应体系中完成上述3个生物元件的酶切和连接,因此该技术被称作"One-POT".插入上述人工转录单元的穿梭质粒导入大肠杆菌和运动发酵单胞菌后可检测到发出绿色荧光的细胞.结果显示通过Golden gate方法可有效组装转录单元所需DNA生物元件.本研究不仅可为运动发酵单胞菌合成生物学和代谢工程研究,尤其是设计多基因代谢途径组装方面提供技术工具,也可为评估运动发酵单胞菌内源启动子和终止子提供一种有效方法.

摘要：In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG gate, New gate and Fredkin gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

摘要：Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

摘要：10-kV 4 H–SiC p-channel insulated gate bipolar transistors(IGBTs) are designed, fabricated, and characterized in this paper. The IGBTs have an active area of 2.25 mm^2 with a die size of 3 mm× 3 mm. A step space modulated junction termination extension(SSM-JTE) structure is introduced and fabricated to improve the blocking performance of the *** SiC p-channel IGBTs with SSM-JTE termination exhibit a leakage current of only 50 nA at-10 kV. To improve the on-state characteristics of SiC IGBTs, the hexagonal cell(H-cell) structure is designed and compared with the conventional interdigital cell(I-cell) structure. At an on-state current of 50 A/cm^2, the voltage drops of I-cell IGBT and H-cell IGBT are10.1 V and 8.3 V respectively. Meanwhile, on the assumption that the package power density is 300 W/cm^2, the maximum permissible current densities of the I-cell IGBT and H-cell IGBT are determined to be 34.2 A/cm^2 and 38.9 A/cm^2 with forward voltage drops of 8.8 V and 7.8 V, respectively. The differential specific on-resistance of I-cell structure and H-cell structure IGBT are 72.36 m?·cm^2 and 56.92 m?·cm^2, respectively. These results demonstrate that H-cell structure silicon carbide IGBT with SSM-JTE is a promising candidate for high power applications.

摘要：两位前辈,一个谈吐诙谐,一个平实沉稳,他们背后,是整个MSQ Partners的现在与未来。两个人就这样淡淡描述着他们对新开张的上海The gate office的期许,举重若轻。完全感觉不到作为最高决策人应有的焦虑或压力。如果我们能从他们精彩的人生和把工作当做乐趣的态度里得到少许启迪,想必已足够。

摘要：JR塔(JR Tower)位于札幌市中央区,原是明治时代的停车场,历史上经过5次大的改造和扩建后完成.本次建设从2000年1月开始到2003年1月竣工,3月正式对外开放.

摘要：狄运昌，曾被亚太区Campaign Magazine评选为大中华年度最佳创意人．原The gate大中华区主席兼创意长。曾担任台湾智威汤逊执行创意总监，带领团队连续多年在各大国内外广告奖赢得不计其数的广告奖．并两度赢得台湾风云广告代理商的头衔。