摘要：This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.

摘要：A wireless communication system can be tested either in actual conditions or by a hardware simulator reproducing actual conditions. With a hardware simulator it is possible to freely simulate a desired type of a radio channel and making it possible to test “on table” mobile radio equipment. This paper presents an architecture for the digital block of a hardware simulator of MIMO propagation channels. This simulator can be used for LTE and WLAN IEEE 802.11ac applications, in indoor and outdoor environments. However, in this paper, specific architecture of the digital block of the simulator is presented to characterize a scenario indoor to outdoor using TGn channel models. The switching between each environment in the scenario must be made in a continuous manner. Therefore, an algorithm is designed to pass from a considered impulse response in the environment to another in other environment. The architecture of the digital block of the hardware simulator is presented and implemented on a Xilinx Virtex-IV FPGA. Moreover, the impulse responses are transferred into the simulator. The accuracy, the occupation on the FPGA and the latency of the architecture are analyzed.

摘要：Synthetic biology is the process of forward engineering living *** systems can be used to produce biobased materials,agriculture,medicine,and *** approach to designing these systems is to employ techniques from the design of embedded *** techniques include abstraction,standards,modularity,automated design,and formal semantic models of ***,these elements form the foundation of“biodesign automation,”where software,robotics,and microfluidic devices combine to create exciting biological systems of the *** paper describes a“hardware,software,wetware”codesign vision where software tools can be made to act as“genetic compilers”that transform high-level specifications into engineered“genetic circuits”(wetware).This is followed by a process where automation equipment,welldefined experimental workflows,and microfluidic devices are explicitly designed to house,execute,and test these circuits(hardware).These systems can be used as either massively parallel experimental platforms or distributed bioremediation and biosensing ***,scheduling and control algorithms(software)manage these systems’actual execution and data analysis tasks.A distinguishing feature of this approach is how all three of these aspects(hardware,software,and wetware)may be derived from the same basic specification in parallel and generated to fulfill specific cost,performance,and structural requirements.

摘要：The ever-increasing need for high performance in scientific computation and engineering applications will push high-perfornlance computing beyond the exascale. As an integral part of a supercomputing system, high- performance processors and their architecture designs are crucial in improving system performance. In this paper, three architecture design goals for high-performance processors beyond the *** are introduced, including effective performance scaling, efficient resource utilization, and adaptation to diverse applications. Then a high-performance many-core processor architecture with scalar processing and application-specific acceleration （Massa） is proposed, which aims to achieve the above three goals by employing the techniques of distributed computational resources and application-customized hardware. Finally, some future research directions regarding the Massa architecture are discussed.

摘要：The software system, hardware system and performance principle of the gas detector were briefly described. A new method was developed for orientating and cali- brating the instrument. The method shows excellence in automation and intelligence, and presents simpler and more reliable new method for orientating and calibrating the nominal physical quantity of the nonlinear sensor.

摘要：Taking a specific production process as an example, this paper introduces the design of multi slot and unequal temperature PID controller based on single chip microcomputer. The mathematical implementation method of PID algorithm and the design method of the hardware and software are discussed, The principle diagram of the hardware circuit implementing the control algorithm and the features of the software possessed are also presented.

摘要：引言　　3D打印，亦称“增材制造”（ additive manufacturing ），是制造业领域正在迅速发展的一项新兴技术，被誉为“具有工业革命意义的制造技术”［1］22。开源硬件②（ open source hardware ）是以类似于开源软件③（ open source soft-ware）的方式设计的硬件，其作用在于鼓励硬件的源代码（即产品设计文件）由硬件设计者、制造者和消费者组成的共享社区内开放分享。从3D打印产业的发展现状来看，正是有了3D 打印设备中的开源硬件（ open source hardware），才使得3D打印机的成本大幅降低，使其从昂贵的、复杂的工业化用途向易于操作、成本低廉的大众化、个性化消费发展［1］27-28。开源硬件许可证是以著作权为基础，构建具有法律约束力的许可协议，并通过许可协议约定源代码的许可方式以及复制、改编行为的界限，规制源代码共享社区中的许可行为和侵权行为。相比开源软件取得的巨大成功，开源硬件仍然裹足不前，缺乏有效和可强制执行的著作权许可协议制约其发展。3D打印技术的出现，为解决开源硬件的这一问题提供了契机。本文拟分析3D打印开源硬件许可证的著作权基础，并探讨3D打印开源硬件的许可方式。

摘要：This paper is concerned with the sensor nodes’ hardware design of the wireless sensor *** focus on the electromagnetic compatibility design of the printed circuit *** this paper,we will give a schematic diagram first,and then,according to the layout,wiring rules and the knowledge of electromagnetic compatibility, we will present the design of the printed circuit board which has a good characteristic of electromagnetic compatibility.

摘要：In order to adjust the beam time structure and convert the continuous wave beam into a pulsed one,a server hardware system based on FPGA and W5300 Ethernet interface is designed,and the client interface running on PC is designed with the help of Visual Sdudio development *** pulse voltage output with adjustable delay,variable cycle and pulse width can be made at either single pulse mode or continuous pulse *** a long term test,the system worked reliably and stably,and the precision of output pulse time can reach 20 ns,which meets system requirements.

摘要：目的 设计一种用于电阻抗断层成像技术(EIT)测量的正交序列解调电路用以检测被测信号的模量和相位.方法 利用DSP Builder,在matlab/simulink中搭建模型文件(.mdl),并利用仿真激励验证方法与设计的正确性和合理性;再用Signal Compiler模块读取建模文件,生成VHDL文件和工具命令语言脚本,在Quartus Ⅱ中进行综合、适配、仿真和硬件实现.结果 仿真和测试结果均表明,所设计的正交序列解调电路能够有效提取被测信号的实部信息和虚部信息,在实验误差允许的范围内能很好满足EIT测量的要求.结论 基于DSP Builder的正交序列解调方法与电路设计能够给出EIT实部和虚部信息,为全信息复阻抗测量提供有力的技术支持.