摘要：As feature size scales down, reliability issues like single event upset(SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10 T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10 T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.

摘要：The design of low-power LVDS（low voltage differential signaling） transceiver ICs is *** LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/*** the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS *** addition,the LVDS receiver also supports the failsafe *** transceiver chips were verified with the CSMC 0.5-μm CMOS *** measured results showed that,for the LVDS transmitter with the pre-charge technique proposed,the maximum data rate is higher than 622 Mb/*** power consumption is 6 mA with a 5-V power *** LVDS receiver can work properly with a larger input common mode voltage（0.1-2.4 V） but a differential input voltage as low as 100 mV The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/*** chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.

摘要：The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit （OEIC） receiver are reported. Each channel of the receiver consists of a photodetector, a transimpedance amplifier,and a post-amplifier. The double photodiode structure speeds up the receiver but hinders responsivity. The adoption of active inductors in the TIA circuit extends the - 3dB bandwidth to a higher level. The receiver has been realized in a CSMC 0.6μm standard CMOS process. The measured results show that a single channel of the receiver is able to work at bit rates of 0.8- 1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

摘要：A series of experiments and numerical simulations are carried out in a high-speed axial compressor to systematically investigate the influence and underlying flow mechanisms of micro tip injection on enhancing compressor *** geometric structures of micro tip injection have been investigated,including the axial positions of injector port,injected mass flow rate and injector ***,seven designed micro tip injection structures and one solid wall casing are tested in the compressor test rig to elucidate the influence of different micro tip injection parameters on the compressor ***,numerical simulations are conducted to analyze the underlying flow mechanisms of micro tip injection with different design parameters on enhancing the compressor *** experimental and numerical investigation reveal that when the injection port is located upstream of the low-speed region,the compressor stability is significantly *** tip injection with larger injected mass flow can obtain higher stall margin *** injector diameter produces higher injection momentum and velocity,contributing to greater improvement on the compressor stability.

摘要：A multiplexer with a low-distortion high-bandwidth analog switch is presented. The gate-to-source voltage of the switch is set by the combined on-voltage of a pMOS and an nMOS,and the difference between its gate-source voltage and the threshold voltage （VGST） is guaranteed to be constant with input variation. Thus, the body effect is nearly canceled. Implemented in a TSMC 0.18μm CMOS process, results from HSPICE simulation show that the VGST is nearly constant with an input range from 0.3 to 1.7V,and the - 3dB bandwidth is larger than 10GHz;the SFDR （spurious free dynamic range） of the output is 67. lldB with 1GHz input frequency; the turn-on time is 2.98ns,and the turn-off time is 1.35ns, which indicates a break-before-make action of the multiplexer. The proposed structure can be applied to high speed signal transmission.

摘要：A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm^2.

摘要：high-speed high-resolution analog-to-digital （A/D） conversion demanded by ultra wideband （UWB） signal processing is a very challenging problem. This paper proposes a parallel random projection method for UWB signal acquisition. The proposed method can achieve high sampling rate, high resolution and technical feasibility of hardware implementation. In the proposed method, an analog UWB signal is projected over a set of random sign functions. Then the low-rate high-resolution analog-to-digital convertors （ADCs） are used to sample the projection coefficients. The signal can be reconstructed by simple linear calculation with the sampling matrix, without complying with optimization algorithm and prior knowledge. In other aspects, unlike other approaches that need to utilize an accurate time-shift at extremely high frequency, or design a hybrid filter bank, or generate specific basis functions or work for signals with prior knowledge, the proposed method is a universal sampling approach and easy to apply. The simulation results of signal to noise ratio （SNR） and spurious-free dynamic range （SFDR） validate the efficiency of the proposed method for UWB signal acquisition.

摘要：The main design factors which effect on operating speed of solenoid actuator for valve operation are mass of plunger, electromagnetic motive force, inductance and return spring, and these factors are not independent but related with each other in view point of design and electromagnetic theory. It is impossible to increase the operating speed by only change the value of any one design factor. The change of any one value results in change of any value related it in various design factors. Permanent magnets are as assistant materials which make higher flux density in air gap. Electromagnetic motive force in controlled only by current. This paper presents a speed increasing design method of solenoid actuator using a solenoid, by some governing equations which are composed of electromagnetic theory and empirical knowledge, and proved the propriety by experiments.

摘要：A RTD-based TSRAM cell is *** mechanism of different types of access transistors in this cell is described and NMOS is found most suitable from consideration of the cell size and power *** architecture of a TSRAM system is *** results show that the RTD-based TSRAM has advanced characteristics of small area,low power,and high speed.

摘要：A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.