摘要：A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.

摘要：A limiting amplifier IC implemented in 65nm CMOS technology and intended for high-speed op- tical fiber communications is described in this paper. The inductorless limiting amplifier incorporates 5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance, a high speed output buffer with novel third order active feedback, and a high speed full-wave rectifier. The re- ceiver signal strength indictor （RSSI） can detect input signal power with 33dB dynamic range, and the limiting amplifier features a programmable loss of signal （LOS） indication with external resistor. The sensitivity of the limiting amplifier is 5.5mV at BER = 10^ -12 and the layout area is only 0.53 × 0.72 mm^2 because of no passive inductor. The total gain is over 41dB, and bandwidth exceeds 12GHz with 56mW power dissipation.

摘要：A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is *** inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise *** a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below *** measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or *** chip area is only 0.70mm×*** to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.