摘要：The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization. In the present paper, a new approach for modeling semicon- ductor devices, nanoscale double gate DG MOSFETs, by use of the gradual channel approximation （GC） approach and genetic algorithm optimization technique （GA） is presented. The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction, to achieve reliable, accurate and simple compact models for nanoelectronic circuit simulations. Our compact models give good predictions of the quantum capacitance, threshold voltage shift, quantum inversion charge density and drain current. These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrrdinger equations. The developed models can also be incorporated into nanoelectronic cir- cuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.

摘要：An analytical investigation has been proposed to study the subthreshold behavior ofjunctionless gates all around （JLGAA） MOSFET for nanoscale CMOS analog applications. Based on 2-D analytical analysis, a new subthreshold swing model for short-channel JLGAA MOSFETs is developed. The analysis has been used to calculate the subthreshold swing and to compare the performance of the investigated design and conventional GAA MOSFET, where the comparison of device architectures shows that the JLGAA MOSFET exhibits a superior performance with respect to the conventional inversion-mode GAA MOSFET in terms of the fabrication process and electrical behavior in the subthreshold domain. The analytical models have been validated by 2-D numerical simulations. The proposed analytical models are used to formulate the objectives functions. The overall objective function is formulated by means of a weighted sum approach to search the optimal electrical and dimensional device parameters in order to obtain the better scaling capability and the electrical performance of the device for ultra-low power applications.