摘要：With the critical charge reduced to generate a single event effect （SEE） and high working frequency for a nanometer integrated circuit, the single event effect （SET） becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n＋ guard ring and p＋ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient （SET） pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET＇s pulse- width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV-cm2/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETefr from 12.5 ***2/mg to 79.5 MeV-cm2/mg and the pulse-width presents saturation tendency when the effective linear energy transfer （LETeff value is larger than 40 MeV-cm2/mg. The test results also show that the hardened commercial standard cell＇s pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.

摘要：Using Technology Computer-Aided Design(TCAD) 3-D simulation,the single event effect(SEE) of 25 nm raised source-drain FinFET is *** on the calibrated 3-D models by process simulation,it is found that the amount of charge collected increases linearly as the linear energy transfer(LET) increases for both n-type and p-type FinFET hits,but the single event transient(SET) pulse width is not linear with the incidence LET and the increasing rate will gradually reduce as the LET *** impacts of wafer thickness on the charge collection are also analyzed,and it is shown that a larger thickness can bring about stronger charge *** reducing the wafer thickness could mitigate the SET effect for FinFET technology.