摘要：研究了JPEG2000算术编码器的算法和电路实现.提出了重归一化规程的一种新的顺序结构,通过添加独立的总移位次数预测规程,使得编码算法可以一次性顺序完成当前上下文的处理.据此设计了具有从流水线的三级流水线电路结构,流水线用于处理无编码字节输出的常规情况,从流水线单独处理编码字节的输出,从而有效缩短了各级电路的关键路径延时.基于TSMC 0.18μm工艺的综合结果表明,系统时钟频率为578MHz,吞吐量约为520 Msym-bols/s.与采用相同工艺的国内外研究成果相比,分别提升了40%和26%以上.

摘要：分别利用0 35μm CMOS工艺和0 2μm GaAs PHEMT(pseudomorphic high electron mobility transistor)工艺实现了激光驱动器集成电路,其工作速率分别为2 5Gb/s和 10Gb/s,可应用于光纤通信 SDH(synchronous dig ital hierarchy)传输系统.

摘要：A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.

摘要：This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier,which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode. Experimental results indicate that with a parasitical capacitance of 2pF,this circuit works at 1.25Gb/s. A clear eye diagram is obtained with an input optical signal of - 17dBm. With a power supply of 3.3V, the front-end amplifier consumes 122mW and provides a 660mV differential output.

摘要：用TSMC 0.18μm CMOS工艺设计了一种应用于5 GHz锁相环型频率合成器中的电荷泵电路.该电路运用单位增益运放电路和自偏置共源共栅电流源电路实现了充放电流的高度匹配.充分利用单位增益运放电路减小电荷泵输出端的电荷共享现象,使电荷泵电路结构较简单并减小了功耗.Spectre后仿真表明,在电源1.8 V、输出电压0.5-1.3 V,充放电流失配率小于0.8%,电流绝对值偏移率小于0.6%,最大功耗8.53 mW.

摘要：采用全开关状态的延时单元和双延时路径两种电路技术设计了一种高工作频率、低相位噪声的环形振荡器。环路级数采用偶数级来获得两路相位相差90°的正交输出时钟,芯片采用台湾TSMC0.18μmCMOS工艺。测试结果表明,振荡器在5GHz的工作频率上,在偏离主频10MHz处相位噪声可达-89.3dB/Hz。采用1.8V电源电压时,电路的功耗为50mW,振荡器核芯面积为60μm×60μm。

摘要：介绍采用0.18μm CMOS工艺设计并实现的光纤通信接收机时钟恢复电路预处理器。核心电路采用乘法器加LC选频器的结构。测试结果表明,该电路可工作在10Gb/s 的输入速率上。

摘要：采用TSMC公司标准的0.18μm CMOS工艺,结合锁相环和延迟锁相环技术,设计并制作了一个全集成的2.5Gbps/ch并行时钟数据恢复电路.与传统并行数据恢复电路相比,该电路不需要本地参考时钟,并且恢复出的并行数据是位同步的.输入2路并行的231-1PRBS数据,恢复出的2.5GHz时钟的均方抖动值为2.6ps,恢复出的两路2.5Gb/s数据的均方抖动值分别为3.3ps和3.4ps.

摘要：基于 DRM 标准,研究并设计了一种 DRM 广播接收机射频前端芯片的结构,该射频前端选用了上边注入、固定中频的二次正交混频低中频结构。经理论推导,给出了该结构的4种镜像抑制比(IRR)与相位误差或幅度误差的定量关系。经综合考虑镜像干扰、互调干扰、低频本振谐波干扰、寄生低频噪声等因素与中频频率的定量或定性关系,确定了系统频率规划。该结构中除射频滤波器外其它模块均为片上实现,继承了低中频结构的所有优点。理论分析与仿真结果表明,采用该频率规划的接收机射频前端完全满足 DRM接收机射频前端的设计要求。此频率规划设计为射频前端芯片的电路级设计成功奠定了理论基础。

摘要：A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed. The model parameters are extracted with high precision, mainly based on analytical methods. The developed model enables fast and accurate time domain transient analysis and noise analysis in RFIC simulation since all elements in the model are fre- quency independent. The validity of the proposed model has been demonstrated by a fabricated monolithic stacked trans- former in TSMC＇s 0.13μm mixed-signal （MS）/RF CMOS＇ process.