摘要：To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is *** input to the scheme is an unscheduled data flow graph (DFG),and timing or resource *** is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout *** is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection *** time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the *** with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.