摘要：This paper presents a universal field programmable gate array（FPGA） programmable routing circuit,focusing primarily on a delay *** the precondition of the routing resource＇s flexibility and routability,the number of programmable interconnect points（PIP） is reduced,and a multiplexer（MUX） plus a BUFFER structure is adopted as the programmable ***,the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit,*** of the above features ensure that the whole FPGA chip is highly repeatable,and the signal delay is uniform and predictable over the total ***,the BUFFER driver is optimized to decrease the signal delay by up to 5%.The proposed routing circuit is applied to the Fudan programmable device（FDP） FPGA,which has been taped out with an SMIC 0.18-μm logic 1P6M *** test result shows that the programmable routing resource works correctly,and the signal delay over the chip is highly uniform and predictable.

摘要：A novel FPGA chip FDP2008 （Fudan Programmable Logic） has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX ＋ Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 ×30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.

摘要：This paper describes the analysis and design of a 0.13 #m CMOS tunable receiver front-end that supports 8 TDD LTE bands, covering the 1.8-2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes. The novel zero-IF receiver core consists of a tunable narrow- band variable gain low-noise amplifier （LNA）, a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier, an LO divider, a rough gain step variable gain pre-amplifier, a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier. The LNA can be tuned by reconfiguring the output parallel LC tank to the responding frequency band, eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes. The test chip is implemented in an SMIC 0.13μm 1PSM CMOS process. The full receiver achieves 4.6 dB NF, -14.5 dBm out of band IIP3, 30-94 dB gain range and consumes 54 mA with a 1.2 V power supply.

摘要：A novel toggled flip-flop（TFF） divide-by-two circuit（DTC） and its optimization method based on a large-signal analysis approach are *** reducing the output RC constant in tracking mode and making it large in latching mode,compressing the internal signal swing as well as compensating the current leaked in the latching mode, the operating frequency range is greatly *** in a SMIC 0.13μm RF CMOS process with a 1.2 V power supply,it can work under an ultra-wide frequency band ranging from 320 MHz to 29.6 *** results show that two phase-locked loops（PLLs） with the proposed DTC can achieve in-band phase noise of-94 dBc/Hz @ 10 kHz under 4224 MHz operating frequency and-84 dBc/Hz @ 10 kHz under 10 GHz operating frequency,respectively. The power consumption of the proposed DTC is reduced by almost 50%compared with the conventional counterparts.

摘要：The analysis and design of a semi-passive radio frequency identification（RFID） tag is *** studying the power transmission link of the backscatter RFID system and exploiting a power conversion efficiency model for a multi-stage AC-DC charge pump,the calculation method for semi-passive tag＇s read range is *** to different read range limitation factors,an intuitive way to define the specifications of tag＇s power budget and backscatter modulation index is given.A test chip is implemented in SMIC 0.18μm standard CMOS technology under the guidance of theoretical *** main building blocks are the threshold compensated charge pump and low power wake-up circuit using the power triggering wake-up *** proposed semi-passive tag is fully compatible to EPC C1G2 *** has a compact chip size of 0.54 mm^2,and is adaptable to batteries with a 1.2 to 2.4 V output voltage.

摘要：A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms （0.48-2000 Hz）. The chip is fabricated via a SMIC 0.18μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.

摘要：A rally integrated receiver RF front-end that meets WCDMA/GSM system requirements is *** supports SAW-less operation for *** improve the linearity in terms of both IP3 and IP2,the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization,current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs.A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle *** addition,a constant-g_m biasing with an on-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the *** RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13μm *** measurement results show that owing to this high-linearity RF front-end,the receiver achieves -6 dBm IIP3 and better than ＋60 dBm IIP2 for all modes and bands.

摘要：A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is *** mismatch and current noise contribution from the CMFB circuit is *** order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling *** calculation result agrees well with the *** on the noise analysis,many methods to lower output current noise of the FDCP are *** fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm *** measured output reference spur is–64 dBc to–69 *** in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.

摘要：This paper presents a 1.12 Gb/s 11.3 mW transmitter using 0.18μm mixed signal complementary metal- oxide semiconductor technology with a 1.8 V supply voltage. This transmitter implements a high-speed transmission with 1.2 V common-mode output voltage, adopting a low-voltage differential signaling （LVDS） technique. A multiplexer （MUX） and an LVDS driver are critical for a transmitter to complete a high-speed data transmission. This paper proposes a high power-efficiency single-stage 14 ： 1 MUX and an adjustable LVDS driver circuit, capable of driving different loads with a slight increase in power consumption. The prototype chip implements a transmitter with a core area of 970 × 560μm2, demonstrating low power consumption and adjustable driving capability.

摘要：A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm^2.