摘要：This paper presents a novel method that is applied to realize the Linear Transformation(LT)Switched-Capacitor Filter(SCF).It adopts the Voltage Control Voltage Source(VCVS)equalized transfor-mation to revise the original LC ladder filter and induce it into 16 basic sections and then extend the princi-ple of the LT in order to fit active and 3 port networks and give out switched-capacitor circuits corre-sponding to the 16 basic sections,which can realize all four kinds of filters——LP,HP,BP,BS ***-signed examples are given *** Nth order filter only requires N amplifiers and the circuit is insensitive toparasitic *** experimental results of a 3rd order elliptic LP and a 6th order elliptic BP are giv-en and agree with the theory.

摘要：Solar cells based on perovskites have emerged as a transpiring technology in the field of photovoltaic. These cells exhibit high power conversion efficiency. The perovskite material is observed to have good absorption in the entire visible spectrum which can be well illustrated by the quantum efficiency curve. In this paper, theoretical analysis has been done through device simulation for designing solar cell based on mixed halide perovskite. Various parameters have efficacy on the solar cell efficiency such as defect density, layer thickness, doping concentration, band offsets, etc. The use of copper oxide as the hole transport material has been analyzed. The analysis divulges that due to its mobility of charge carriers, it can be used as an alternative to spiro-OMeTAD. With the help of simulations, reasonable materials have been employed for the optimal design of solar cell based on perovskite material. With the integration of copper oxide into the solar cell structure, the results obtained are competent enough. The simulations have shown that with the use of copper oxide as hole transport material with mixed halide perovskite as absorber, the power conversion efficiency has improved by 6%. The open circuit voltage has shown an increase of 0.09 V, short circuit current density has increased by 2.32 mA/cm2, and improvement in fill factor is 8.75%.

摘要：In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.

摘要：Spatio-temporal databases aim at appropriately managing moving objects so as to support various types of queries. While much research has been conducted on developing query processing techniques, less effort has been made to address the issue of when and how to update location information of moving objects. Previous work shifts the workload of processing updates to each object which usually has limited CPU and battery capacities. This results in a tremendous processing overhead for each moving object. In this paper, we focus on designing efficient update strategies for two important types of moving objects, free-moving objects(FMOs) and network-constrained objects(NCOs), which are classified based on object movement models. For FMOs, we develop a novel update strategy, namely the FMO update strategy(FMOUS), to explicitly indicate a time point at which the object needs to update location information. As each object knows in advance when to update(meaning that it does not have to continuously check), the processing overhead can be greatly reduced. In addition, the FMO update procedure(FMOUP) is designed to efficiently process the updates issued from moving objects. Similarly, for NCOs, we propose the NCO update strategy(NCOUS) and the NCO update procedure(NCOUP) to inform each object when and how to update location information. Extensive experiments are conducted to demonstrate the effectiveness and efficiency of the proposed update strategies.

摘要：A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first *** gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） *** is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped ***,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） *** is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.

摘要：In multiple-input multiple-output （MIMO） systems, space-time block codes （STBCs） from orthogonal designs （ODs） and coordinate interleaved orthogonal designs （CLOD） have been attracting wider attention due to their amenability for fast （single symbol） maximum-likelihood （ML） decoding, and full-rate with full-rank over quasi-static fading channels. However, most of these codes, for transmitting antennas more than 4, have large number of zero entries in their codeword matrix. Due to the zero entries in the design, the transmitting antennas need to be switched on and off imposing severe hardware constraints. To solve this problem, we propose a method to generate a new class of no-zero-entry single symbol maximum likelihood decodable STBCs （NZESSDCs）, which is based on coordinate interleaving and group precoding technique. The ability of the proposed group precoding based NZESSDCs （called G-NZESSDCs） on single symbol ML Decoding and full diversity are analyzed and derived. The performance evaluation is accomplished by numerical simulation and is compared with recently reported NZESSDCs （called C-NZESSDCs）. Compared with C-NZESSDCs, the proposed G-NZESSDCs have same bit-error-rate （BER） performance and better peak-to-average ratio （PAPR） performance.

摘要：Single-symbol maximum-likelihood （ML） decodable space-time block codes （SSDCs） can achieve a maximal symbol rate of 6/7 for multiple-input multiple-output （MIMO） communication system with five or six transmit antennas by using rate-efficient generalized coordinate interleaved orthogonal designs （RE-GCIODs）. Unfortunately, there are many zero entries in the eodeword matrix of RE-GCIODs. The zero entries result in high peak-to-average power ratio （PAPR） and also impose a severe constraint on hardware implementation. In this paper, for MIMO communication systems with five or six transmit antennas and one receive antenna, a new SSDC is proposed. By combining Alamouti code and orthogonal space-time block code （OSTBC）, desirable properties like RE-GCIODs can be achieved and are derived, including maximal symbol rate up to 6/7, full diversity and single-symbol ML decodability. Moreover, by reducing the number of zero entries in the codeword matrix, the peak-to-average power ratio （PAPR） of our proposed code is lower than RE-GCIODs. Simulation results show that the proposed codes outperform RE-GCIODs under peak power constraint while performing almost same under average power constraint.

摘要：Modern wireless communications gadgets demand multi-standard communications facilities with least overlap between different input radio channels. A sharp digital filter of extremely narrow transition-width with lower stop band ripples offers alias-free switching among the preferred frequency bands. A computationally competent low pass filter (LPF) structure based on the multistage frequency response masking (FRM) approach is proposed for the design of sharp finite impulse response (FIR) filters which are suitable for wireless communications applications. In comparison of basic FRM with other existing multistage FRM structures, the proposed structure has a narrow transition bandwidth and higher stop band attenuation with significant reduction in terms of the number of computational steps. A design example is incorporated to demonstrate the efficiency of the proposed approach. Simulation results establish the improvement of the proposed scheme over other recently published design strategies.

摘要：A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.

摘要：A three-part comb decimator is presented in this paper, for the applications with severe requirements of circuit performance and frequency response. Based on the modified prime factorization method and multistage polyphase decomposition, an efficient non-recursive structure for the cascaded integrator-comb （CIC） decimation filter is derived. Utilizing this structure as the core part, the proposed comb decimator can not only loosen the decimation ratio＇s limitation, but also balance the tradeoff among the overall power consumption, circuit area and maximum speed. Further, to improve the frequency response of the comb decimator, a cos-prefilter is introduced as the preprocessing part for increasing the aliasing rejection, and an optimum sin-based filter is used as the compensation part for decreasing the passband droop.