摘要：Various efficient generalized sphere decoding (GSD) algorithms have been proposed to approach optimal ML performance for underdetermined linear systems, by transforming the original problem into the full-column-rank one so that standard SD can be fully applied. However, their design parameters are heuristically set based on observation or the possibility of an ill-conditioned transformed matrix can affect their searching efficiency. This paper presents a better transformation to alleviate the ill-conditioned structure and provides a systematic approach to select design parameters for various GSD algorithms in order to high efficiency. Simulation results on the searching performance confirm that the proposed techniques can provide significant improvement.

摘要：Memristor is a newly found fourth circuit element for the next generation emerging nonvolatile memory technology. In this paper, design of new type of nonvolatile static random access memory cell is proposed by using a combination of memristor and complemented metal oxide semiconductor. Biolek memristor model and CMOS 180 nm technology are used to form a single cell. By introducing distinct binary logic to avoid safety margin is left for each binary logic output and enables better read/write data integrity. The total power consumption reduces from 0.407 mw (milli-watt) to 0.127 mw which is less than existing memristor based memory cell of the same CMOS technology. Read and write time is also significantly reduced. However, write time is higher than conventional 6T SRAM cell and can be reduced by increasing motion of electron in the memristor. The change of the memristor state is shown by applying piecewise linear input voltage.

摘要：LTE (Long Term Evolution) is the latest technology in wireless communication. It is being used because of its peak data rate and spectral efficiency. LTE uses OFDMA (Orthogonal Frequency Division Multiple Access) technology for radio transmission and reception in downlink. OFDM is a multicarrier modulation and multiplexing technique to improve data rate, spectral efficiency and minimize the problem of fading and ISI (Inter Symbol Interference). Many transceivers design have been designed for OFDM system to minimize error and maximize throughput of the information being transmitted and received at the system. The purpose of this article is to present a survey of the published literature which deals with various OFDM transceiver design, focusing on the merits and demerits of the corresponding OFDM transceiver design.

摘要：The main research objective in wireless sensor networks (WSN) domain is to develop algorithms and protocols to ensure minimal energy consumption with maximum network lifetime. In this paper, we propose a novel design for energy harvesting sensor node and cross-layered MAC protocol using three adjacent layers (Physical, MAC and Network) to economize energy for WSN. The basic idea behind our protocol is to re-energize the neighboring nodes using the radio frequency (RF) energy transmitted by the active nodes. This can be achieved by designing new energy harvesting sensor node and redesigning the MAC protocol. The results show that the proposed cross layer CL_EHSN improves the life time of the WSN by 40%.

摘要：Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 - 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

摘要：Content Addressable Memory (CAM) is a type of memory used for high-speed search applications. Due to parallel comparison feature, the CAM memory leads to large power consumption which is caused by frequent pre-charge or discharge of match line. In this paper, CAM for automatic charge balancing with self-control mechanism is proposed to control the voltage swing of ML for reducing the power consumption of CAM. Another technique to reduce the power dissipation is to use MSML, it combines the master-slave architecture with charge minimization technique. Unlike the conventional design, only one match line (ML) is used, whereas in Master-Slave Match Line (MSML) one master ML and several slave MLs are used to reduce the power dissipation in CAM caused by match lines (MLs). Theoretically, the match line (ML) reduces the power consumption up to 50% which is independent of search and match case. The simulation results using Cadence tool of MSML show the reduced power consumption in CAM and modified CAM cell.

摘要：针对多子阵合成孔径声呐(SAS)成像运算量大及忽略相位误差导致的成像效果不佳等缺点,该文在深入分析了多子阵SAS的两类系统相位误差基础上,分别提出了改进的逐点和逐线成像算法,形成了新的多子阵SAS系统方案设计。新方法在提高测绘率同时,能够显著降低运算量并改善成像效果,仿真实验也证明了新方法的正确性。

摘要：Minimum Partial Euclidean Distance (MPED) based K-best algorithm is proposed to detect the best signal for MIMO (Multiple Input Multiple Output) detector. It is based on Breadth-first search method. The proposed algorithm is independent of the number of transmitting/receiving antennas and constellation size. It provides a high throughput and reduced Bit Error Rate (BER) with the performance close to Maximum Likelihood Detection (MLD) method. The main innovations are the nodes that are expanded and visited based on MPED algorithm and it keeps track of finally selecting the best candidates at each cycle. It allows its complexity to scale linearly with the modulation order. Using Quadrature Amplitude Modulation (QAM) the complex domain input signals are modulated and are converted into wavelet packets and these packets are transmitted using Additive White Gaussian Noise (AWGN) channel. Then from the number of received signals the best signal is detected using MPED based K-best algorithm. It provides the exact best node solution with reduced complexity. The pipelined VLSI architecture is the best suited for implementation because the expansion and sorting cores are data driven. The proposed method is implemented targeting Xilinx Virtex 5 device for a 4 × 4, 64-QAM system and it achieves throughput of 1.1 Gbps. The results of resource utilization are tabulated and compared with the existing algorithms.

摘要：Optical logic gates are elementary components for optical network and optical computing. In this paper, we propose a structure for AND, NAND, XNOR and NOR logic gates in the two dimensional photonic crystal which utilizes the dispersion based self-collimation effect. The self-collimated beam is splitted by the line defect and interfered with other self-collimated beam. This interference may be constructive or destructive based on their phase difference. This phenomenon is employed to realize all-optical logic gates. The gates are demonstrated numerically by computing electromagnetic field distribution using the finite difference time domain （FDTD） method. The results ensure that this design can function as AND, NAND, XNOR and NOR logic gates. The size of the structure is about 10 μm× 10 μm which in turn results in an increase in the speed and all the gates are realized in the same configuration. The ON-OFF contrast ratio is about 6 dB.

摘要：Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 22 = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.