摘要：Interference alignment(IA) is suitable for cognitive radio networks(CRNs).However, in IA spectrum sharing(SS) process of general underlay CRNs, transmit power of cognitive radio transmitters usually should be reduced to satisfy interference constraint of primary user(PU), which may lead to low signalto-noise-ratio at cognitive radio receivers(CRRs). Consequently, sum rate of cognitive users(CUs) may fall short of the theoretical maximum through IA. To solve this problem,we propose an adaptive IA SS method for general distributed multi-user multi-antenna CRNs. The relationship between interference and noise power at each CRR is analyzed according to channel state information, interference requirement of PU, and power budget of CUs. Based on the analysis, scenarios of the CRN are classified into 4 cases, and corresponding IA SS algorithms are properly designed. Transmit power adjustment, CU access control and adjusted spatial projection are used to realize IA among CUs. Compared with existing methods, the proposed method is more general because of breaking the restriction that CUs can only transmit on the idle sub-channels. Moreover, in comparison to other five IA SS methods applicable in general CRN, the proposed method leads to improved achievable sum rate of CUs while guarantees transmission of PU.

摘要：Two kinds of lattice-basis reduction precoding schemes based on successive interference cancellation are *** successive interference cancellation(SIC) structure can be obtained by either orthogonal and a right triangular matrix(QR) decomposition,or the Vertical Bell Labs Layered Space Time(VBLAST) algorithm which provides optimal user ***,the extended channel approach is applied to the proposed SIC-based *** results show that the proposed schemes can achieve comparable BER performance to vector precoding(VP).

摘要：Efficient reconfigurable field programmable gate array （FPGA） architectures for the MD6-224/256/384/512 Hash algorithm are proposed in this article. The basic iterative compact design requires 923 ALMs and achieves a throughput ranging from 225 Mbit/s to 394 Mbit/s at a maximum frequency of 198 MHz. The 32-step-urtrolled high-throughput design requires 7 090 ALMs and achieves a throughput ranges from 5 776 Mbit/s to 9 490 Mbit/s at a maximum frequency of 173 MHz. The simulation results show that high flexibility and efficient FPGA implementation of the MD6 Hash function is achieved.

摘要：A High birefringence microstructure fiber with four big elliptical air holes is investigated by using the finite-difference frequency-domain (FDFD) method. Based on the numerical simulations, the influence of the air-hole size and pitch upon the mode birefringence is analyzed. The work may be helpful for the design and fabrication of high birefringence PCFs.

摘要：An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and *** adder determines the overall performance of the circuits in most of those *** this paper we propose a novel 1-bit full adder cell which uses only eight *** this design,three multiplexers and one inverter are applied tominimize the transistor count and reduce power *** power dissipation,propagation delay,and power-delay produced using the new design are analyzed and com-pared with those of other designs using HSPICE *** results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) *** low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.

摘要：A flat-top interleaver,in which a mirror on one arm of the Michelson interferomefer is replaced by a G-T resonator,is *** the interleaver,the parameters including the channel spacing of 50 GHz,ripple less than 0.05 dB,-0.5 dB passband of 43 GHz(86% of the spacing),-30 dB stopband of 42 GHz(84% of the spacing),and a channel isolation higher than 40 dB,are achieved.

摘要：The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.

摘要：In Discrete Multi-Tone (DMT) modulation systems, the well-known technique to overcome the Inter-Carrier Interference (ICI)/Inter-Symbol Interference (ISI) caused by the inadequate Cyclic Prefix (CP) length is to use a Time-Domain Equalizer (TDE) at the receiver front-end. An algorithm used to calculate the coefficients of the optimal shortening Time Domain Equalizer (TDE) was given by Melsa. However, this algorithm requires that the length of the TDE must be smaller than or equal to the memory length of the target impulse response. This paper modifies this algorithm and makes it not only fit for calculating the coefficients of the TDE with arbitrary length, but also have a much less computational time.

摘要：A novel ASM one-zero-hot design method based upon ternary flip-flops with binaryconstruction as storage cells is presented.

摘要：Multi-service SDH networks support both packet- and circuit-switched traffic. Optimal design of such a network means to guarantee the circuit connections and configure a logical packet-switched topology with lowest congestion. This letter first formulates the problem as a mixed integer linear programming, which achieves optimal solution but has high computation. Then a heuristic algorithm is proposed to yield near-optimal solution efficiently. Performance of the algorithm is verified by an example.