摘要：This paper presents the key optimization techniques for an efficient accelerator implementation in an image encoder IP core design for real-time Joint Photographic Experts Group Lossless(JPEG-LS) *** architecture and accelerator elements have been utilized to enhance the throughput *** parameters mapping schemes and resource sharing have been adopted for the purpose of low complexity and small chip die ***-level and fine-grained gating measures have been used to achieve a low-power *** has been proved that these hardware-oriented optimization techniques make the encoder meet the requirements of the IP core *** proposed optimization techniques have been verified in the implementation of the JPEG-LS encoder IP,and then validated in a real wireless endoscope system.

摘要：All digital implementation of receiver is a main topic on digital communication recently. The design of interpolation filter is one of the important problems for all digital implementation of receiver. In this paper, for full response linear modulation signal, a interpolation criterion is proposed. An interpolation formula is presented on bandwidth-limited transmission signal. For example, using the raised cosine roll off function as the system pulse response, the feasibility and effectiveness on the interpolation formula are certified by theoretical and numerical analysis. The computer simulation result on 16-QAM signal is given.

摘要：The device structure and technical processings of quasi-planar self-aligned silicon avalanche electron emission array arc introduced. The processing step at the edge of electron emission region is about 10nm only and the width of self-aligned current channel of shallow As implantation is about 3μm. Its I-V characteristics show a larger linear region and lower series resistance than that of the previous silicon avalanche electron emission devices. Some of the electron emission characteristics are also discussed in this paper.

摘要：Based on the property that high degree variable nodes within an irregular LowDensity Parity-Check (LDPC) code have more powerful error-correcting capability than that of low degree variable nodes, a group of irregular LDPC codes with Unequal Error Protection (UEP)property is designed in this letter. Simulation results show that the transmission quality of the image may be effectively improved with this class of irregular LDPC code.

摘要：We present several design examples of how to apply transformation optics and curved space under coordinate transformation to manipulating the surface plasmon waves in a controlled *** demonstrate in detail the design procedure of the plasmonic wave squeezer,in-plane bend and omnidirectional *** show that the approximation method of modifying only the dielectric material of a dielectric-metal surface of the plasmonic device could lead to acceptable performance,which facilitates the fabrication of the *** functionality of the proposed plasmonic device is verified using three-dimensional full-wave electromagnetic *** at practical realization,we also show the design of a plasmonic in-plane bend and omnidirectional absorber by an alternative transformation scheme,which results in a simple device structure with a tapered isotropic dielectric cladding layer on the top of the metal surface that can be fabricated with existing nanotechnology.

摘要：A new idea to design fibre-based digital autocorrelation technique for completely characterizing ultrashort pulses is presented. Feasibility of the design is demonstrated by theory. The technique is found to promise minimized optical alignment requirements, compact configuration, high time resolution, and short measurement time.

摘要：A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.

摘要：Since digital circuits have been widely and thoroughly applied in various fields, electronic systems are increasingly more complicated and require greater reliability. Faults may occur in electronic systems in complicated environments. If immediate field repairs are not made on the faults, electronic systems will not run normally, and this will lead to serious losses. The traditional method for improving system reliability based on redundant fault-tolerant technique has been unable to meet the requirements. Therefore, on the basis of(evolvable hardware)-based and(reparation balance technology)-based electronic circuit fault self-repair strategy proposed in our preliminary work, the optimal design of rectification circuits(RTCs) in electronic circuit fault self-repair based on global signal optimization is deeply researched in this paper. First of all, the basic theory of RTC optimal design based on global signal optimization is proposed. Secondly, relevant considerations and suitable ranges are analyzed. Then, the basic flow of RTC optimal design is researched. Eventually, a typical circuit is selected for simulation verification, and detailed simulated analysis is made on five circumstances that occur during RTC evolution. The simulation results prove that compared with the conventional design method based RTC, the global signal optimization design method based RTC is lower in hardware cost, faster in circuit evolution, higher in convergent precision, and higher in circuit evolution success rate. Therefore, the global signal optimization based RTC optimal design method applied in the electronic circuit fault self-repair technology is proven to be feasible, effective, and advantageous.

摘要：A stable 10 GHz ultrashort pulse generator consisted of an electroabsorption modulator （EAM） and a welldesigned fibre-based pulse compressor is proposed and demonstrated experimentally. The obtained short pulse has high extinction ratio, no pedestal, low timing jitter, and FWHM of only 2.4ps. The excellent performance of multiplexing from 10 GHz to 160 GHz confirms the potential of the generator for applications in 160 Gbit/s optical time-division-multiplexing （OTDM） systems.

摘要：A 512-bit EEPROM IP was designed by using just logic process based *** limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were *** addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving ***,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were *** reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was *** result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.