摘要：Two-dimensional （2D） elliptically cylindrical invisible cloaks with multiple regions are designed based on the trans-formation optics and the complementary media theory. Multiple invisible cloak regions can be obtained by properly using the compressed or folded transformation in each space layer. The constitutive parameter tensor expressions for each re- gion have been obtained. The results of full wave simulations by using finite element software confirm the validity of the constitutive parameter tensor expressions. In addition, the parameters are relatively easier to realize.

摘要：This paper presents a low quiescent current,highly stable low-drop out（LDO） *** order to reduce capacitor value and control frequency response peak,capacitor multipliers are adopted in the compensation circuit with mathematic *** phase margin is adequate when the load current is 0.1 or 150 *** in an XFAB 0.6μm CMOS process,the LDO produces 12.2 mV（0.7%） overshoot voltage while the current changes at 770 mA/100μs with a capacitor load of 10μF.

摘要：To meet the requirements of the low power Zigbee system, VCO design optimizations of phase noise, power consumption and frequency tuning are discussed in this paper. Both flicker noise of tail bias transistors and up-conversion of flicker noise from cross-coupled pair are reduced by improved self-switched biasing technology, leading to low close-in phase noise. Low power is achieved by low supply voltage and triode region biasing. To linearly tune the frequency and get constant gain, distributed varactor structure is adopted. The proposed VCO is fabricated in SMIC 0.18-#m CMOS process. The measured linear tuning range is from 2.38 to 2.61 GHz. The oscillator exhibits low phase noise of-77.5 dBc/Hz and -122.8 dBc/Hz at l0 kHz and 1 MHz offset, respectively, at 2.55 GHz oscillation frequency while dissipating 2.7 mA from 1.2 V supply voltage, which well meet design specifications.

摘要：A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.

摘要：We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method,having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V,simulation results showed that the charge time is 35 ns in the proposed sense amplifier,and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications,and has a silicon area of only 240 μm2.

摘要：Efficient reconfigurable field programmable gate array （FPGA） architectures for the MD6-224/256/384/512 Hash algorithm are proposed in this article. The basic iterative compact design requires 923 ALMs and achieves a throughput ranging from 225 Mbit/s to 394 Mbit/s at a maximum frequency of 198 MHz. The 32-step-urtrolled high-throughput design requires 7 090 ALMs and achieves a throughput ranges from 5 776 Mbit/s to 9 490 Mbit/s at a maximum frequency of 173 MHz. The simulation results show that high flexibility and efficient FPGA implementation of the MD6 Hash function is achieved.

摘要：A time-to-digital convener （TDC） oaseo on a reset-tree anti anti-harmonic oelay-locKeo oop （DLL） circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid ＂false locking＂. Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18μm CMOS technology, and its core area occupies 0.7 x 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than 4-0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.

摘要：A new method for patterned sapphire substrate （PSS） design is developed and proven to be reliable and cost-effective. As progress is made with LEDs＇ luminous efficiency, the pattern units of PSS become more complicated, and the effect of complicated geometrical features is almost impossible to study systematically by experiments only. By employing our new method, the influence of pattern parameters can be systematically studied, and various novel patterns are designed and optimized within a reasonable time span, with great improvement in LEDs＇ light extraction efficiency （LEE）. Clearly, PSS pattern design with such a method deserves particular attention. We foresee that GaN-based LEDs on these newly designed PSSs will achieve more progress in the coming years.

摘要：A simple integrated coupler is proposed for the efficient excitation of surface plasmon polariton （SPP） mode in a thin metal film. The SPP mode is generated in a single Ag-dielectric interface by the incident field and coupled with an Ag thin film. The coupling efficiency at different wavelengths using two different dielectrics, gallium lanthanum sulfide （GLS） and aluminum gallium arsenide （AIGaAs） is calculated by analyzing the SPP propagation dynamics with the finite difference time domain method. A maximum coupling efficiency of 70~ is obtained at a wavelength of 46Ohm when GLS is used, whereas the corresponding value obtained for A1GaAs is 60~o at 56Onto. The proposed structure can be used to excite SPPs in a nano-thin film from an external bulky source and is easier to fabricate since a single interface metal-dielectric configuration is used to excite the metal-thin film.

摘要：With the development of Ethernet systems and the growing capacity of modem silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethemet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Intemet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system＇s throughput. Our simulation results showed that the maximum throughput of Ethemet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethemet, and that using only one chip can realize that many electronic devices access to the Intemet directly and get high performance.