摘要：This paper describes the design and development of the timer based on liquid level measurement system in which timer 555 is used in astable mode. The capacitor charging time i. e. the ON time pulse width of the timer output waveform which is measured using a digital storage oscillator （DSO）,is linearly proportional to the capacitance of a co-axial cylindrical capacitive transducer, and this capacitance once again linearly varies with the change in liquid level. Hence, we obtain a linear relationship between the liquid level and the capacitor charging time. The main advantages of this developed system are linear input-output relationship, small in size, easily portable, cost effective, and independent on the ambient temperature effect. The system can also be exploited to measure dielectric constant of liquid or solid in various process industries.

摘要：The design and development of a timer based revolution per minute(RPM)measurement system were described in this *** rotating shaft of a dc motor was used to measure the RPM and timer integrated circuit(IC)555 was used in astable *** frequency of timer output waveform measured by a digital storage oscilloscope(DSO)is almost linearly proportional to the RPM of rotating shaft,and the RPM also linearly varies with the change of the external input voltage *** the linear relationship between the frequency of timer output waveform and the RPM can be *** main advantages of this developed system are linear input-output relationship,small size,easy to carry and cost effective.

摘要：This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.

摘要：Recently, the use of ubiquitous sensor network technology has spread vastly. The ubiquitous sensor networks are widely de- ployed in factory auttxnation as they provide effective measuring solution for instruments. The wired/wireless network module, which provides the interface to connect to the u-sensor network, is needed but there is no perfect standardization about the interface. In this situation, the interface compatibility between measuring instrument can be maintained using the IEEEI451 international standard. In this paper, the Wireless Transducer Interface Mcduie （WTIM） based on IEEE1451.5 was designed. It coxnects to the measuring instnmnt, like the muiti-meter, power meter, and etc., to support the RS232 interface. As these devices cannot connect to network without a mod- ule, we use the WTIM to help these devices connect to network sys- ton. Its ftmction was verified through the ubiquitous network connection and data transfer between monitoring PC and measuring instrument. This technology is expected to reduce cost in order to construct the wireless industry automation system using existing devices.

摘要：The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.

摘要：This paper reports design of a CMOS optical receiver front-end using 0.18 μm technology. Design process is current associated with photodiode using trans-impedance amplifier (TIA) for wide bandwidth, high gain, low input referred noise and wide dynamic range. The Automated Gain Control (AGC) voltage is used to provide variable gain for multilevel signals. This design is simulated in 0.18 μm UMC technology for the performance analysis. The best simulation results are reported the maximum TIA gain of 67.26 dB? at 0 V AGC followed by a post amplifier gain of 86.70 dB?. The bandwidth range is 7.03 GHz to 11.5 GHz corresponding to 0 - 3 V AGC respectively. The input referred noise level value is 43.86 pA/√Hz up to 10 GHz frequency. In addition authors have obtained the common mode rejection ratio (CMRR) is 72.42 dB and rectified group delay is 144.48 ps. Verification of the design, reported results are compared with earlier published work and improvements obtained in the present results.