摘要：An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and *** adder determines the overall performance of the circuits in most of those *** this paper we propose a novel 1-bit full adder cell which uses only eight *** this design,three multiplexers and one inverter are applied tominimize the transistor count and reduce power *** power dissipation,propagation delay,and power-delay produced using the new design are analyzed and com-pared with those of other designs using HSPICE *** results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) *** low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.

摘要：A rotary traveling-wave oscillator（RTWO） targeted at 5.8 GHz band operation is designed and fabricated using standard 0.18μm CMOS *** simulation and measurement results are *** chip size including pads is 1.5×1.5 mm^*** measured output power at a frequency of 5.285 GHz is 6.68 dBm,with a phase noise of-102 dBc/Hz at 1 MHz offset from the carrier.

摘要：This study presents a new method of 4-pipelined high-performance split multiply-accumulator (MAC) architecture, which is capable of supporting multiple precisions developed for media processors. To speed up the design further, a novel partial product compression circuit based on interleaved adders and a modified hybrid partial product reduction tree (PPRT) scheme are proposed. The MAC can perform 1-way 32-bit, 4-way 16-bit signed/unsigned multiply or multiply-accumulate operations and 2-way parallel multiply add (PMADD) operations at a high frequency of 1.25 GHz under worst-case conditions and 1.67 GHz under typical-case conditions, respectively. Compared with the MAC in 32-bit microprocessor without interlocked piped stages (MIPS), the proposed design shows a great advantage in speed. Moreover, an improvement of up to 32% in throughput is achieved. The MAC design has been fabricated with Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS standard cell technology and has passed a functional test.

摘要：We propose the spectrum allocation and resource scheduling algorithms in cognitive point to multipoint (PMP) networks with rapid changes of spectrum opportunities and present a media access control (MAC) protocol based on these algorithms. The objective of spectrum allocation is to make efficient use of the spectrum while maintaining the transceiver synchronization on frequency and time in the network. The objective of resource scheduling is to guarantee the quality of service (QoS) requirements of different kinds of connections and to minimize the total energy consumption in the network as well. By sensing only a small set of possible channels in each slot based on the state transition probability of each channel, our spectrum allocation algorithm achieves high spectrum efficiency in the network. The resource scheduling problem is divided into three sub problems and we derive optimal solutions to these problems by greedy algorithm and convex optimization. The simulation results show that our algorithm can make efficient use of the spectrum and the network resources at a cost of low computational complexity.

摘要：The accuracy of microwave ranging is mainly limited by the frequency instability of the oscillator that generates the carrier phase signal. A dual transponder carrier ranging method is used to minimize the oscillator noise by combining the reference and the to-and-fro measurements. This ranging approach together with pseudo-noise ranging or other means can be used to measure the inter-satellite distance with a high precision. The pseudo-noise ranging system or other ranging systems help to solve the integer circles while the dual transponder ranging system guarantees the accurate fractional circle. The two satellites work in the master-slave mode. The range measurements are derived on the master satellite while the slave satellite just coherently transfers the received signal, so that the dual transponder ranging system does not need to rely on the time tagging system to synchronize the two satellites. This study first describes the dual transponder carrier ranging system and shows how the system removes most of the oscillator noise components effectively. Then, a detailed design scheme on the frequency planning of the ranging system is presented and the supporting analysis illustrates the feasibility of this system. Based on the design innovation, a laboratory demonstration system is assembled to verify the realizability of the dual transponder ranging system. The experimental results demonstrate that a high level of accuracy (about 30 μm under laboratory circumstance) can be achieved by the use of the proposed dual transponder carrier ranging system.

摘要：Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.

摘要：Efficient reconfigurable field programmable gate array （FPGA） architectures for the MD6-224/256/384/512 Hash algorithm are proposed in this article. The basic iterative compact design requires 923 ALMs and achieves a throughput ranging from 225 Mbit/s to 394 Mbit/s at a maximum frequency of 198 MHz. The 32-step-urtrolled high-throughput design requires 7 090 ALMs and achieves a throughput ranges from 5 776 Mbit/s to 9 490 Mbit/s at a maximum frequency of 173 MHz. The simulation results show that high flexibility and efficient FPGA implementation of the MD6 Hash function is achieved.

摘要：In application of tomography imaging, limited-angle problem is a quite practical and important *** this paper, an iterative reprojection-reconstruction(IRR) algorithm using a modified Papoulis-Gerchberg(PG)iterative scheme is developed for reconstruction from limited-angle projections which contain noise. The proposed algorithm has two iterative update processes, one is the extrapolation of unknown data, and the other is the modification of the known noisy observation data. And the algorithm introduces scaling factors to control the two processes, respectively. The convergence of the algorithm is guaranteed, and the method of choosing the scaling factors is given with energy constraints. The simulation result demonstrates our conclusions and indicates that the algorithm proposed in this paper can obviously improve the reconstruction quality.

摘要：Datapath accounts for a considerable part of power consumption in VLSI circuit design. This paper presents a method for physical implementation of datapath to achieve low power consumption. Regularity is a characteristic of datapath and the key of the proposed method, where synthesis is tightly combined with placement to make full use of regularity, so that low power consumption is achieved. In This paper, a new concept of Synthesis In Relative Placement (SIRP) is given to deal with the semi-regularity in some datapath. Experimental results of a sample circuit validated the proposed method.

摘要：A novel mapping equivalent approach is proposed in this paper, which can be used for analyzing and realizing a memristor-based dynamical circuit equivalently by a nonlinear dynamical circuit with the same topologies and circuit parameters. A memristor-based chaotic circuit and the corresponding Chua＇s chaotic circuit with two output differentiators are taken as examples to illustrate this approach. Equivalent dynamical analysis and realization of the memristor-based chaotic circuit are performed by using Chua＇s chaotic circuit. The results indicate that the outputs of memristor-based chaotic circuit and the corresponding outputs of Chua＇s chaotic circuit have identical dynamics. The proposed approach verified by numerical simulations and experimental observations is useful in designing and analyzing memristor-based dynamical circuits.