摘要：In this paper we present a motion compensation (MC) design for the newest Audio Video coding Standard (AVS) of China. Because of compression-efficient techniques of variable block size (VBS) and sub-pixel interpolation, intensive pixel calculation and huge memory access are required. We propose a parallel serial filtering mixed luma interpolation data flow and a three-stage multiplication free chroma interpolation scheme. Compared to the conventional designs, the integrated architecture supports about 2.7 times filtering throughput. The proposed MC design utilizes Vertical Z processing order for reference data re-use and saves up to 30% memory bandwidth. The whole design requires 44.3k gates when synthesized at 108 MHz clock frequency using 0.18-μm CMOS technology and can support up to 1920×1088@30 fps AVS HDTV video decoding.

摘要：The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.