摘要：Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.

摘要：A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M rf- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V.

摘要：This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.

摘要：This paper presents a low noise amplifier（LNA）,which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13μm rf-CMOS *** circuit was analyzed and a new optimization method for a folded cascode LNA was *** results of the proposed circuit demonstrated a power gain of 14.13 dB,consuming 3 mW DC power,showing 1.96 dB NF and an input 1-dB compression point of -19.9 *** input power matching（S_（11）） and output power matching（S_（22）） were below -10 *** results indicate that this LNA is fully applicable to low voltage and low power applications.

摘要：This paper presents a differential low power low noise amplifier designed for the wireless sensor network （WSN） in a TSMC 0.18μm rf CMOS process.A two-stage cross-coupling cascaded common-gate（CG） topology has been designed as the *** first stage is a capacitive cross-coupling *** can reduce the power and noise *** second stage is a positive feedback cross-coupling topology,used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA.A differential inductor has been designed as the load to achieve reasonable *** inductor has been simulated by the means of momentum electromagnetic simulation in ADS.A ＂double-π＂ circuit model has been built as the inductor model by iteration in *** inductor has been fabricated separately to verify the model. The LNA has been fabricated and *** LNA works well centered at 2.44 *** measured gain S_（21） is variable with high gain at 16.8 dB and low gain at 1 *** NF（noise figure） at high gain mode is 3.6 dB,the input referenced 1 dB compression point（IP1dB） is about -8 dBm and the IIP3 is 2 dBm at low gain *** LNA consumes about 1.2 mA current from 1.8 V power supply.

摘要：A gallium nitride(GaN)power amplifier monolithic microwave integrated circuit(MMIC)with a wide band and high efficiency in the microwave frequency band is proposed in this *** power amplifier MMIC uses a 0.15^im GaN high electron mo-bility transistor(HEMT)*** operating frequency band of the amplifier can cover the whole K-band,i.e.,17-26.5 GHz.