摘要：This paper presents an embedded SRAM design for write buffer applications in flash *** write buffer is implemented with a newly proposed self-adaptive timing co.trol circuit,an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory *** simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.