摘要：According to the requirements of the bus terminal regulator,a linear regulator with 3-A source-sink current ability is *** use of the NMOS pass transistor and load current feedback technique enhances the system current ability and response *** method of adaptive zero compensation realizes loop stability over the whole load range for either source or sink ***,the transconductance matching technique reduces the shoot-through current through the output stage to less than 3μ*** regulator has been fabricated with a 0.6-μm 30 V BCD process successfully,and the area size is about 1 mm;.With a 20μF output capacitor, the maximum transient output-voltage variation is within 3.5%of the output voltage with load step changes of±2 A/lμ*** the load range of±3 A,the variation of output voltage is less than±15 mV.

摘要：A novel anti-jamming integrated CMOS current-sensing circuit for current-mode buck regulators is presented. Based on the widely-used traditional current-sensing structure, anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit. Also the transient response is faster through the introduction of current offset. The circuit is concise, simple to implement and suits for SoC applications with single power supply. A dualoutput current-mode DC-DC buck converter with proposed structure has been fabricated with a 0.5 μm CMOS process for validation. In the 2.5–5.5 V input range, the two channels work steadily in the load current range of 0–600 mA. And the measured maximum efficiency is up to 96%.

摘要：A buck DC-DC switching regulator with high efficiency is implemented by automatically altering the modulation mode according to load current,and it can operate with an input range of 4.5 to 30 *** light load current,the converter operates in skip *** converter enters PWM mode operation with increasing load *** reduces the switching loss at light load and standby state,which results in prolonging battery lifetime and stand-by ***, externally adjustable soft-start minimizes the inrush supply current and avoids the overshoot of output voltage at initial *** regulator is fabricated by a 0.6μm CDMOS *** test results show that,under the condition of 3.3 V output,the efficiency is up to 64%at 5 mA and the maximum efficiency is 95.5%.

摘要：Accurate and fast performance estimation is necessary to drive design space exploration and thus support important design decisions. Current techniques are either time consuming or not accurate enough. In this paper, we solve these problems by presenting a hybrid method for multimedia multiprocessor system-on-chip （MPSoC） performance estimation. A general coverage analysis tool GNU gcov is employed to profile the execution statistics during the native simulation. To tackle the complexity and keep the analysis and simulation manageable, the orthogonalization of communication and computation parts is adopted. The estimation result of the computation part is annotated to a transaction accurate model for further analysis, by which a gradual refinement of MPSoC performance estimation is supported. The implementation and its experimental results prove the feasibility and efficiency of the proposed method.