摘要：This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15 μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz. This chip is composed of a single ended-into differential-out active Balun, balanced FETs in push-push configuration, and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power, and the fundamental frequency suppression is typically -20 dBc up to 44 GHz. The MMIC works at VDD = 3.5 V, Vss = -3.5 V, Id = 200 mA and the chip size is 1.5× 1.8 mm^2.

摘要：A 53 GHz Colpitts oscillator implemented in a SiGe：C BiCMOS technology is presented. Limited by a 26.5 GHz frequency analyzer, the oscillator was measured indirectly through an on-chip mixer. The mixer downconverted the oscillating frequency to an intermediate frequency （IF） below 26.5 GHz. By adjusting the local oscillating （LO） frequency and recording the changes of IF frequency, the oscillator＇s output frequency （rf） was determined. Additionally, using phase noise theory of mixers, the oscillator＇s phase noise was estimated as -58 dBc/Hz at 1 MHz offset and the output power was about -21 dBm. The chip is 270 ×480μm in size.

摘要：The design of low-power LVDS（low voltage differential signaling） transceiver ics is *** LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/*** the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS *** addition,the LVDS receiver also supports the failsafe *** transceiver chips were verified with the CSMC 0.5-μm CMOS *** measured results showed that,for the LVDS transmitter with the pre-charge technique proposed,the maximum data rate is higher than 622 Mb/*** power consumption is 6 mA with a 5-V power *** LVDS receiver can work properly with a larger input common mode voltage（0.1-2.4 V） but a differential input voltage as low as 100 mV The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/*** chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.

摘要：An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm rfCMOS *** circuit comprises a 3rd-order active-RC complex filter（CF） and a programmable gain amplifier（PGA）.An automatic tuning circuit is also designed to tune the CF＇s pass *** of the class-A fully differential operational amplifier（FDOPA） adopted in the conventional CF and PGA design,a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current *** the PGA circuit,a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly.A reformative switching network is proposed,which can eliminate the switch resistor＇s influence on the gain accuracy of the *** measurement result shows the gain range of the circuit is 10-50 dB with a 1-dB step size,and the gain accuracy is less than ±0.3 *** OIP3 is 23.3 dBm at the gain of 10 *** results show that the settling time is reduced from 100 to 1 *** image band rejection is about 40 *** only draws 4.5 mA current from a 1.8 V supply voltage.

摘要：A low noise distributed amplifier consisting of 9 gain cells is *** chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor（PHEMT） technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and *** measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz *** noise figure is between 2 and 4.1 dB during the band from 2 to 20 *** amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point（IIP3）,which demonstrates the excellent performance of *** power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm^2.

摘要：A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET（IMOS） varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range（FTR） of 18.4%and a phase noise of –101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.

摘要：A limiting amplifier IC implemented in 65nm CMOS technology and intended for high-speed op- tical fiber communications is described in this paper. The inductorless limiting amplifier incorporates 5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance, a high speed output buffer with novel third order active feedback, and a high speed full-wave rectifier. The re- ceiver signal strength indictor （RSSI） can detect input signal power with 33dB dynamic range, and the limiting amplifier features a programmable loss of signal （LOS） indication with external resistor. The sensitivity of the limiting amplifier is 5.5mV at BER = 10^ -12 and the layout area is only 0.53 × 0.72 mm^2 because of no passive inductor. The total gain is over 41dB, and bandwidth exceeds 12GHz with 56mW power dissipation.

摘要：A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.

摘要：This paper presents the design of a 26-40 GHz monolithic doubly-balanced mixer for high-speed wireless communication. A modified Marchand balun is used to expand the bandwidth. A coupled line of the U section improves the port to port isolation and provides the IF-output port. The mixer was simulated and fabricated in 0.15-μm GaAs PHEMT technology;the measurement results agree well with the simulation *** mixer achieves low conversion loss of 5.9 to 8.6 dB and high isolation over a 26-40 GHz rf/LO bandwidth and a DC-14 GHz IF bandwidth.

摘要：A low-noise amplifier （LNA） operated at 40 GHz is designed. An improved cascode configuration is proposed and the design of matching networks is presented. Short-circuited coplanar waveguides （CPWs） were used as inductors to achieve a high Q-factor. The circuit was fabricated in a 0.13-μm SiGe BiCMOS technology with a transistor transit frequency fT of 103 GHz. The chip area is 0.21mm^2. The LNA has one cascode stage with a-3 dB bandwidth from 34 to 44 GHz. At 40 GHz, the measured gain is 8.6dB; the input return loss, S11, is -16.2dB; and the simulated noise figure is 5 dB. The circuit draws a current of only 3 mA from a 2.5 V supply.